UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 302

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

302
(4) TMQ0 I/O control register 1 (TQ0IOC1)
The TQ0IOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIQ00
to TIQ03 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TQ0IOC1
After reset: 00H
Cautions 1. Rewrite
TQ0IS7
TQ0IS5
TQ0IS3
TQ0IS1
TQ0IS7
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
7
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
R/W
TQ0IS6
TQ0IS6
TQ0IS4
TQ0IS2
TQ0IS0
2. The TQ0IS7 to TQ0IS0 bits are valid only in the free-
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
6
TQ0CTL0.TQ0CE bit = 0. (The same value can be written
when the TQ0CE bit = 1.)
performed, clear the TQ0CE bit to 0 and then set the bits
again.
running timer mode and the pulse width measurement
mode.
possible.
Preliminary User’s Manual U18953EJ1V0UD
Address:
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
TQ0IS5
Capture trigger input signal (TIQ02 pin) valid edge detection
Capture trigger input signal (TIQ03 pin) valid edge setting
Capture trigger input signal (TIQ01 pin) valid edge setting
Capture trigger input signal (TIQ00 pin) valid edge setting
In all other modes, a capture operation is not
5
the
TQ0IS4
FFFFF543H
TQ0IS7
4
TQ0IS3
to
3
If rewriting was mistakenly
TQ0IS0
TQ0IS2
2
bits
TQ0IS1
1
when
TQ0IS0
0
the