UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 419

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) Real-time output buffer registers 0L, 0H (RTBL0, RTBH0)
Note After setting the real-time output port, set output data to the RTBL0 and RTBH0 registers by the time a real-
4 bits × 1 channel,
2 bits × 1 channel
6 bits × 1 channel
The RTBL0 and RTBH0 registers are 4-bit registers that hold preset output data.
These registers are mapped to independent addresses in the peripheral I/O register area.
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
If an operation mode of 4 bits × 1 channel or 2 bits × 1 channel is specified (RTPC0.BYTE0 bit = 0), data can
be individually set to the RTBL0 and RTBH0 registers. The data of both these registers can be read at once
by specifying the address of either of these registers.
If an operation mode of 6 bits × 1 channel is specified (BYTE0 bit = 1), 8-bit data can be set to both the RTBL0
and RTBH0 registers by writing the data to either of these registers. Moreover, the data of both these
registers can be read at once by specifying the address of either of these registers.
Table 12-2 shows the operation when the RTBL0 and RTBH0 registers are manipulated.
Operation Mode
time output trigger is generated.
RTBL0
RTBH0
Cautions 1. When writing to bits 6 and 7 of the RTBH0 register, always set 0.
After reset: 00H
Table 12-2. Operation During Manipulation of RTBL0 and RTBH0 Registers
2. Accessing the RTBL0 and RTBH0 registers is prohibited in the following
RTBL0
RTBH0
RTBL0
RTBH0
0
Register to Be
Manipulated
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)
statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O
registers.
• When the CPU operates with the subclock and the main clock oscillation is
• When the CPU operates with the internal oscillation clock
stopped
R/W
0
Preliminary User’s Manual U18953EJ1V0UD
Address: RTBL0 FFFFF6E0H, RTBH0 FFFFF6E2H
RTBH05 RTBH04
RTBH0
RTBH0
RTBH0
RTBH0
Higher 4 Bits
Read
RTBL0
RTBL0
RTBL0
RTBL0
RTBL03 RTBL02
Lower 4 Bits
Invalid
RTBH0
RTBH0
RTBH0
Higher 4 Bits
RTBL01
RTBL00
Write
RTBL0
Invalid
RTBL0
RTBL0
Note
Lower 4 Bits
419