IC MCU 128K 4MHZ A/D LV 64TQFP

ATMEGA103L-4AC

Manufacturer Part NumberATMEGA103L-4AC
DescriptionIC MCU 128K 4MHZ A/D LV 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103L-4AC datasheets
 


Specifications of ATMEGA103L-4AC

Core ProcessorAVRCore Size8-Bit
Speed4MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature0°C ~ 70°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Features
®
Utilizes the AVR
RISC Architecture
AVR – High-performance and Low-power RISC Architecture
– 121 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Up to 6 MIPS Throughput at 6 MHz
Data and Nonvolatile Program Memory
– 128K Bytes of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 4K Bytes Internal SRAM
– 4K Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
– SPI Interface for In-System Programming
Peripheral Features
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– Programmable Serial UART
– Master/Slave SPI Serial Interface
– Real-time Counter (RTC) with Separate Oscillator
– Two 8-bit Timer/Counters with Separate Prescaler and PWM
– Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare,
Capture Modes and Dual 8-, 9-, or 10-bit PWM
– Programmable Watchdog Timer with On-chip Oscillator
– 8-channel, 10-bit ADC
Special Microcontroller Features
– Low-power Idle, Power-save and Power-down Modes
– Software Selectable Clock Frequency
– External and Internal Interrupt Sources
Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
Power Consumption at 4 MHz, 3V, 25°C
– Active: 5.5 mA
– Idle Mode: 1.6 mA
– Power-down Mode: < 1 µA
I/O and Packages
– 32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines
– 64-lead TQFP
Operating Voltages
– 2.7 - 3.6V for ATmega103L
– 4.0 - 5.5V for ATmega103
Speed Grades
– 0 - 4 MHz for ATmega103L
– 0 - 6 MHz for ATmega103
8-bit
Microcontroller
with 128K Bytes
In-System
Programmable
Flash
ATmega103
ATmega103L
Note:
Not recommended in new
designs.
Rev. 0945I–AVR–02/07
1

ATMEGA103L-4AC Summary of contents

  • Page 1

    ... Programmable I/O Lines, 8 Output Lines, 8 Input Lines – 64-lead TQFP • Operating Voltages – 2.7 - 3.6V for ATmega103L – 4.0 - 5.5V for ATmega103 • Speed Grades – MHz for ATmega103L – MHz for ATmega103 8-bit Microcontroller with 128K Bytes In-System Programmable Flash ...

  • Page 2

    Pin Configuration ATmega103(L) 2 TQFP (AD2 (AD1 (AD0 VCC 52 GND 53 (ADC7 (ADC6 (ADC5 (ADC4 (ADC3) ...

  • Page 3

    ... By combining an 8-bit RISC CPU with a large array of ISP Flash on a monolithic chip, the Atmel ATmega103( powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. The ATmega103(L) AVR is supported with a full suite of program and system develop- ment tools including: C compilers, macro assemblers, program debugger/simulators, In- Circuit Emulators and evaluation kits ...

  • Page 4

    Block Diagram ATmega103(L) 4 Figure 1. The ATmega103(L) Block Diagram PF0 - PF7 VCC GND PORTF BUFFERS AVCC ANALOG MUX ADC AGND AREF PROGRAM COUNTER PROGRAM FLASH INSTRUCTION REGISTER REGISTERS INSTRUCTION DECODER CONTROL LINES DATA REGISTER DATA DIR. PORTE REG. ...

  • Page 5

    Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) Port E (PE7..PE0) Port F (PF7..PF0) RESET XTAL1 XTAL2 0945I–AVR–02/07 Supply voltage. Ground. Port 8-bit bi-directional I/O port. Port pins can ...

  • Page 6

    TOSC1 TOSC2 WR RD ALE AVCC AREF AGND PEN Clock Options Crystal Oscillator ATmega103(L) 6 Input to the inverting Timer/Counter Oscillator amplifier. Output from the inverting Timer/Counter Oscillator amplifier. External SRAM write strobe External SRAM read strobe ALE is the ...

  • Page 7

    External Clock Timer Oscillator 0945I–AVR–02/07 To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3. Figure 3. External Clock Drive Configuration EXTERNAL OSCILLATOR SIGNAL For the Timer ...

  • Page 8

    Architectural Overview ATmega103(L) 8 Figure 4. The ATmega103(L) AVR RISC Architecture AVR ATmega103(L) Architecture Program 64K x 16 Counter Program Memory Instruction Register Instruction Decoder Control Lines The AVR uses a Harvard architecture concept – with separate memories and buses ...

  • Page 9

    General Purpose Register File 0945I–AVR–02/07 arate Interrupt Vector in the Interrupt Vector table at the beginning of the Program memory. The different interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher ...

  • Page 10

    X-register, Y-register and Z- register ALU – Arithmetic Logic Unit ISP Flash Program Memory SRAM Data Memory ATmega103(L) 10 The registers R26..R31 have some added functions to their general purpose usage. These registers are address pointers for indirect addressing of ...

  • Page 11

    Figure 7. Memory Configurations Memory Configuration A Program Memory Program Flash (32K/64K x 16) Memory Configuration B Program Memory Program Flash (32K/64K x 16) ATmega103(L) Data Memory $0000 32 Registers $0000 - $001F 64 I/O Registers $0020 - $005F ...

  • Page 12

    Program and Data Addressing Modes ATmega103(L) 12 The 4096 first Data memory locations address both the Register File, the I/O memory and the internal Data SRAM. The first 96 locations address the Register File and I/O memory, and the next ...

  • Page 13

    Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct 0945I–AVR–02/07 Figure 8. Direct Single Register Addressing 15 OP The operand is contained in register d (Rd). Figure 9. Direct Register Addressing, Two Registers 15 9 ...

  • Page 14

    Data Direct Data Indirect with Displacement Data Indirect ATmega103(L) 14 Figure 11. Direct Data Addressing LSBs 15 A 16-bit Data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify the destination ...

  • Page 15

    Data Indirect with Pre- decrement Data Indirect with Post- increment Constant Addressing Using the LPM and ELPM Instructions 0945I–AVR–02/07 Figure 14. Data Indirect Addressing with Pre-decrement 15 X Z-REGISTER The X-, Y-, or the Z-register is decremented before ...

  • Page 16

    Direct Program Address, JMP and CALL Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL ATmega103(L) 16 1). If ELPM is used, LSB of the RAM Page Z register (RAMPZ) is used to select low or high ...

  • Page 17

    EEPROM Data Memory Memory Access Times and Instruction Execution Timing 0945I–AVR–02/07 Program execution continues at address The relative address k is -2048 to 2047. The EEPROM memory is organized as a separate Data space in ...

  • Page 18

    I/O Memory ATmega103(L) 18 The internal Data SRAM access is performed in two System Clock cycles as described in Figure 22. Figure 22. On-chip Data SRAM Access Cycles T1 System Clock Ø Address Prev. Address Data WR Data RD See ...

  • Page 19

    Table 2. ATmega103(L) I/O Space (Continued) I/O Address (SRAM Address) Name $2D ($4D) TCNT1H $2C ($4C) TCNT1L $2B ($4B) OCR1AH $2A ($4A) OCR1AL $29 ($49) OCR1BH $28 ($48) OCR1BL $27 ($47) ICR1H $26 ($46) ICR1L $25 ($45) TCCR2 $24 ...

  • Page 20

    Status Register – SREG ATmega103(L) 20 Table 2. ATmega103(L) I/O Space (Continued) I/O Address (SRAM Address) Name $06 ($26) ADCSR $05 ($25) ADCH $04 ($24) ADCL $03 ($23) PORTE $02 ($22) DDRE $01 ($21) PINE $00 ($20) PINF Note: Reserved ...

  • Page 21

    Stack Pointer – SP 0945I–AVR–02/07 ied into T by the BST instruction and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. • Bit 5 – H: Half-carry ...

  • Page 22

    RAM Page Z Select Register – RAMPZ MCU Control Register – MCUCR ATmega103(L) 22 instruction and it is incremented by 2 when an address is popped from the Stack with return from subroutine RET or return from interrupt RETI. Bit ...

  • Page 23

    XTAL Divide Control Register – XDIV Reset and Interrupt Handling 0945I–AVR–02/07 • Bits 4, 3 – SM1/SM0: Sleep Mode Select Bits 1 and 0 This bit selects between the three available sleep modes as shown in Table 3. Table 3. ...

  • Page 24

    ATmega103(L) 24 higher the priority level. RESET has the highest priority and next is INT0 (the External Interrupt Request 0), etc. Table 4. Reset and Interrupt Vectors Program Vector No. Address Source 1 $0000 RESET 2 $0002 INT0 3 $0004 ...

  • Page 25

    Reset Sources 0945I–AVR–02/07 $0012 jmp TIM2_COMP $0014 jmp TIM2_OVF $0016 jmp TIM1_CAPT $0018 jmp TIM1_COMPA $001A jmp TIM1_COMPB $001C jmp TIM1_OVF $001E jmp TIM0_COMP $0020 jmp TIM0_OVF $0022 jmp SPI_STC $0024 jmp UART_RXC $0026 jmp UART_DRE $0028 jmp UART_TXC $002A ...

  • Page 26

    ATmega103(L) 26 Figure 23. Reset Logic Power-on Reset VCC Circuit RESET Reset Circuit Watchdog PEN D Q Timer E On-chip RC Oscillator XTAL1 POR 14-stage Ripple Counter Q8 Q11 Q13 Delay Unit 0945I–AVR–02/07 ...

  • Page 27

    Power-on Reset 0945I–AVR–02/07 Table 5. Reset Characteristics (V Symbol Parameter Power-on Reset Threshold (rising) (1) V POT Power-on Reset Threshold (falling) V RESET Pin Threshold Voltage RST T Reset Delay Time-out Period TOUT Note: 1. The Power-on Reset will not ...

  • Page 28

    External Reset ATmega103(L) 28 Figure 24. MCU Start-up, RESET Tied POT VCC V RST RESET t TOUT TIME-OUT INTERNAL RESET Figure 25. MCU Start-up, RESET Controlled Externally V POT VCC RESET TIME-OUT INTERNAL RESET An external reset ...

  • Page 29

    Watchdog Reset MCU Status Register – MCUSR 0945I–AVR–02/07 When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura- tion. On the falling edge of this pulse, the delay timer starts counting the Time-out ...

  • Page 30

    Interrupt Handling External Interrupt Mask Register – EIMSK ATmega103( external or Watchdog reset occurs, the source of reset can be found by using the fol- lowing truth table, Table 8. Table 8. Reset Source Identification Reset Source Watchdog ...

  • Page 31

    External Interrupt Flag Register – EIFR External Interrupt Control Register – EICR 0945I–AVR–02/07 • Bits 3..0 – INT3 - INT0: External Interrupt Request Enable When an INT3 - INT0 bit is set (one) and the I-bit in ...

  • Page 32

    ATmega103(L) 32 cuting instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate an interrupt request as long as the pin is held low. 0945I–AVR–02/07 ...

  • Page 33

    Timer/Counter Interrupt Mask Register – TIMSK 0945I–AVR–02/07 Bit 7 6 $37 ($57) OCIE2 TOIE2 TICIE1 Read/Write R/W R/W R/W Initial Value 0 0 • Bit 7 – OCIE2: Timer/Counter2 Output Compare Interrupt Enable When the OCIE2 bit is set (one) ...

  • Page 34

    ATmega103(L) 34 • Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $0020) ...

  • Page 35

    Timer/Counter Interrupt Flag Register – TIFR 0945I–AVR–02/07 Bit 7 6 $36 ($56) OCF2 TOV2 ICF1 Read/Write R/W R/W R/W Initial Value 0 0 • Bit 7 – OCF2: Output Compare Flag 2: The OCF2 bit is set (one) when compare ...

  • Page 36

    Interrupt Response Time Sleep Modes Idle Mode ATmega103(L) 36 (Tim er/Co un ter1 Ove rflow Inte rrup t En able set (o ne Timer/Counter1 Overflow interrupt is executed. In PWM mode, ...

  • Page 37

    Power-down Mode Power-save Mode 0945I–AVR–02/07 When the SM1/SM0 bits are set to 10, the SLEEP instruction makes the MCU enter the Power-down mode. In this mode, the external Oscillator is stopped while the external interrupts and the Watchdog (if enabled) ...

  • Page 38

    Timer/Counters Timer/Counter Prescalers ATmega103(L) 38 The ATmega103(L) provides three general purpose Timer/Counters – two 8-bit T/Cs and one 16-bit T/C. Timer/Counter0 optionally can be asynchronously clocked from an external Oscillator. This Oscillator is optimized for use with a 32.768 kHz ...

  • Page 39

    Timer/Counters T/C0 and T/C2 0945I–AVR–02/07 The clock source for Timer/Counter0 prescaler is named PCK0. PCK0 is by default con- nected to the main system clock CK. Observe that CPU clock frequency can be lower than the XTAL frequency if ...

  • Page 40

    ATmega103(L) 40 Figure 31. Timer/Counter2 Block Diagram T/C2 OVER- FLOW IRQ TIMER INT. MASK REGISTER (TIMSK TIMER/COUNTER2 (TCNT2 8-BIT COMPARATOR 7 0 OUTPUT COMPARE REGISTER2 (OCR2) The 8-bit Timer/Counter0 can select clock source from PCK0 or ...

  • Page 41

    Timer/Counter0 Control Register – TCCR0 Timer/Counter2 Control Register – TCCR2 0945I–AVR–02/07 Bit ($53) – PWM0 COM01 Read/Write R R/W R/W Initial Value Bit $25 ($45) – PWM2 COM21 Read/Write R ...

  • Page 42

    Timer/Counter0 – TCNT0 Timer/Counter2 – TCNT2 ATmega103( PWM mode, this bit has no effect. • Bits – CS02, CS01, CS00/CS22, CS21, CS20: Clock Select Bits 2, 1 and 0 The Clock Select2 bits 2, 1 ...

  • Page 43

    Timer/Counter0 Output Compare Register – OCR0 Timer/Counter2 Output Compare Register – OCR2 Timer/Counters 0 and 2 in PWM Mode 0945I–AVR–02/07 These 8-bit registers contain the value of the Timer/Counters. Both Timer/Counters are realized up/down (in PWM mode) ...

  • Page 44

    Asynchronous Status Register – ASSR ATmega103(L) 44 Figure 32. Effects on Unsynchronized OCR Latching Compare Value changes Synchronized OCR Latch Compare Value changes Unsynchronized OCR Latch During the time between the write and the latch operation, a read from OCR0 ...

  • Page 45

    Asynchronous Operation of Timer/Counter0 0945I–AVR–02/07 • Bit 3 – AS0: Asynchronous Timer/Counter0 When set (one), Timer/Counter0 is clocked from the TOSC1 pin. When cleared (zero), Timer/Counter0 is clocked from the internal system clock, CK. When the value of this bit ...

  • Page 46

    ATmega103(L) 46 • When writing to one of the registers TCNT0, OCR0 or TCCR0, the value is transferred to a temporary register and latched after two positive edges on TOSC1. The user should not write a new value before the ...

  • Page 47

    Timer/Counter1 0945I–AVR–02/07 save mode was entered. After an edge on the asynchronous clock, TCNT0 will read correctly. (The compare and overflow functions of the Timer are not affected by this behavior.) Safe procedure to ensure correct value is read: ...

  • Page 48

    ATmega103(L) 48 Figure 33. Timer/Counter1 Block Diagram T/C1 OVER- T/C1 COMPARE MATCHA IRQ FLOW IRQ TIMER INT. MASK TIMER INT. FLAG REGISTER (TIMSK) REGISTER (TIFR T/C1 INPUT CAPTURE REGISTER (ICR1 TIMER/COUNTER1 (TCNT1 ...

  • Page 49

    Timer/Counter1 Control Register A – TCCR1A 0945I–AVR–02/07 If the Noise Canceler function is enabled, the actual trigger condition for the capture event is monitored over four samples, and all four must be equal to activate the capture flag. Bit 7 ...

  • Page 50

    Timer/Counter1 Control Register B – TCCR1B ATmega103(L) 50 Table 16. PWM Mode Select PWM11 PWM10 Description 0 1 Timer/Counter1 is an 8-bit PWM Timer/Counter1 is a 9-bit PWM Timer/Counter1 is a 10-bit PWM. Bit 7 6 ...

  • Page 51

    Timer/Counter1 – TCNT1H and TCNT1L 0945I–AVR–02/07 • Bits – CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0 The lock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1. Table 17. Clock1 Prescale ...

  • Page 52

    Timer/Counter1 Output Compare Register – OCR1AH and OCR1AL Timer/Counter1 Output Compare Register – OCR1BH and OCR1BL Timer/Counter1 Input Capture Register – ICR1H and ICR1L ATmega103(L) 52 full 16-bit register read operation. When using Timer/Counter1 as an 8-bit Timer ...

  • Page 53

    Timer/Counter1 in PWM Mode 0945I–AVR–02/07 Read/Write Initial Value The Input Capture Register is a 16-bit read-only register. When the rising or falling edge (according to the Input Capture ...

  • Page 54

    ATmega103(L) 54 the value TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A/OCR1B write. See Figure 35 for an example. Figure 35. Effects on Unsynchronized OCR1 Latching Compare Value changes Synchronized OCR1X ...

  • Page 55

    Watchdog Timer Watchdog Timer Control Register – WDTCR 0945I–AVR–02/07 The Watchdog Timer is clocked from a separate On-chip Oscillator. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 21. See characterization data ...

  • Page 56

    ATmega103( the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four ...

  • Page 57

    EEPROM Read/Write Access EEPROM Address Register – EEARH, EEARL EEPROM Data Register – EEDR EEPROM Control Register – EECR 0945I–AVR–02/07 The EEPROM Access Registers are accessible in the I/O space. The write access time is in the range of 2.5 ...

  • Page 58

    ATmega103(L) 58 • Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at ...

  • Page 59

    Prevent EEPROM Corruption 0945I–AVR–02/07 During periods of low V , the EEPROM Data can be corrupted because the supply volt- CC age is too low for the CPU and the EEPROM to operate properly. These issues are the same as ...

  • Page 60

    Serial Peripheral Interface – SPI ATmega103(L) 60 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega103(L) and peripheral devices or between several AVR devices. The ATmega103(L) SPI features include the following: • Full-duplex, Three-wire Synchronous Data ...

  • Page 61

    SS Pin Functionality 0945I–AVR–02/07 Figure 38. SPI Master-Slave Interconnection MSB MASTER 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR The system is single-buffered in the transmit direction and double-buffered in the receive direction. This means that characters to be transmitted cannot be ...

  • Page 62

    Data Modes SPI Control Register – SPCR ATmega103(L) 62 the SS pin is brought high. If the SS pin is brought high during a transmission, the SPI will stop sending and receiving immediately and both data received and data sent ...

  • Page 63

    SPI Status Register – SPSR 0945I–AVR–02/07 • Bit 5 – DORD: Data Order When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the ...

  • Page 64

    ATmega103(L) 64 • Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and will always read as zero. 0945I–AVR–02/07 ...

  • Page 65

    SPI Data Register – SPDR 0945I–AVR–02/07 Bit $0F ($2F) MSB Read/Write R/W R/W R/W Initial Value The SPI Data Register is a read/write register used for data transfer between the Regis- ter File and ...

  • Page 66

    UART Data Transmission ATmega103(L) 66 The ATmega103(L) features a full duplex (separate Receive and Transmit Registers) Universal Asynchronous Receiver and Transmitter (UART). The main features are: • Baud Rate Generator that can Generate a large Number of Baud Rates (bps) ...

  • Page 67

    Figure 41. UART Transmitter DATA BUS BAUD x 16 BAUD RATE XTAL GENERATOR STORE UDR SHIFT ENABLE CONTROL LOGIC IDLE UART CONTROL REGISTER (UCR) On the baud rate clock following the transfer operation to the Shift Register, the start ...

  • Page 68

    Data Reception ATmega103(L) 68 Figure 42. UART Receiver XTAL BAUD X 16 BAUD RATE GENERATOR PIN CONTROL LOGIC DATA RECOVERY RXD LOGIC The Receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud ...

  • Page 69

    Figure 43. Sampling Received Data RXD START BIT D0 D1 RECEIVER SAMPLING When the stop bit enters the Receiver, the majority of the three samples must be one to accept the stop bit. If two or more samples are ...

  • Page 70

    UART Control UART I/O Data Register – UDR UART Status Register – USR ATmega103(L) 70 Bit $0C ($2C) MSB Read/Write R/W R/W R/W Initial Value The UDR Register is actually two physically separate registers ...

  • Page 71

    UART Control Register – UCR 0945I–AVR–02/07 • Bit 4 – FE: Framing Error This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incom- ing character is zero. The FE bit is ...

  • Page 72

    ATmega103(L) 72 • Bit 1 – RXB8: Receive Data Bit 8 When CHR9 is set (one), RXB8 is the ninth data bit of the received character. • Bit 0 – TXB8: Transmit Data Bit 8 When CHR9 is set (one), ...

  • Page 73

    Baud Rate Generator 0945I–AVR–02/07 The baud rate generator is a frequency divider that generates baud rates according to the following equation: BAUD • BAUD = baud rate • CPU clock frequency CK • UBRR = contents of the ...

  • Page 74

    Table 24. UBRR Settings at Various CPU Frequencies Baud Rate 1 MHz %Error 2400 UBRR= 25 4800 UBRR= 12 9600 UBRR= 14400 UBRR= 19200 UBRR= 28800 UBRR= 38400 UBRR= 57600 UBRR= 76800 UBRR= 115200 UBRR= Baud Rate 3.2768 MHz %Error ...

  • Page 75

    Analog Comparator Analog Comparator Control and Status Register – ACSR 0945I–AVR–02/07 The analog comparator compares the input values on the positive input PE2 (AC+) and negative input PE3 (AC-). When the voltage on the positive input PE2 (AC+) is higher ...

  • Page 76

    ATmega103(L) 76 ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logical “1” to the flag. Observe, however, that if another bit in this register is modified using the SBI or CBI instruction, ACI will be ...

  • Page 77

    Analog-to-Digital Converter Feature list: 0945I–AVR–02/07 • 10-bit Resolution • ±2 LSB Absolute Accuracy • 0.5 LSB Integral Non-linearity • 280 µs Conversion Time • kSPS • 8 Multiplexed Input Channels • Interrupt on ADC Conversion ...

  • Page 78

    Operation Prescaling ATmega103(L) 78 The ADC operates in Single Conversion mode, and each conversion will have to be ini- tiated by the user. The ADC is enabled by writing a logical “1” to the ADC Enable bit, ADEN in ADCSR. ...

  • Page 79

    ADEN bit is set and is continuously reset when ADEN is low. When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following falling edge of ...

  • Page 80

    ADC Noise Canceler Function ADC Multiplexer Select Register – ADMUX ADC Control and Status Register – ADCSR ATmega103(L) 80 The ADC features a noise canceler that enables conversion during Idle mode to reduce noise induced from the CPU core. To ...

  • Page 81

    ADC Data Register – ADCL and ADCH 0945I–AVR–02/07 • Bit 5 – Res: Reserved Bit This bit is reserved in the ATmega103(L). Warning: When writing ADCSR, a logical “0” must be written to this bit. • Bit 4 – ADIF: ...

  • Page 82

    ADC Noise Canceling Techniques ATmega103(L) 82 Digital circuitry inside and outside the ATmega103(L) generates EMI, which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. ...

  • Page 83

    ADC DC Characteristics TA = -40°C to 85°C Symbol Parameter Condition Resolution Absolute VREF = 4V, V accuracy ADC clock = 200 kHz Absolute VREF = 4V, V accuracy ADC clock = 1 MHz Absolute VREF = 4V, V ...

  • Page 84

    Interface to External SRAM ATmega103(L) 84 The interface to the SRAM consists of: Port A: multiplexed low-order address bus and data bus Port C: high-order address bus The ALE pin: address latch enable The RD and WR pin: read and ...

  • Page 85

    Figure 51. External SRAM Access Cycle without Wait States System Clock Ø ALE Address [15..8] Prev. Address Data / Address [7..0] Prev. Address WR Data / Address [7..0] Prev. Address RD Figure 52. External SRAM Access Cycle with Wait ...

  • Page 86

    I/O Ports Port A Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port A as General Digital I/O ATmega103(L) 86 All AVR ports have true Read-Modify-Write functionality when ...

  • Page 87

    Port A Schematics Port B 0945I–AVR–02/07 pins are tri-stated when a reset condition becomes active, even if the clock is not running. Table 28. DDAn Effects on Port A Pins DDAn PORTAn I Input 0 1 Input 1 ...

  • Page 88

    Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port B as General Digital I/O ATmega103(L) 88 inputs and are externally pulled low, they will source current if the ...

  • Page 89

    Alternate Functions of Port B 0945I–AVR–02/07 Table 30. DDBn Effects on Port B Pins DDBn PORTBn I Input 0 1 Input 1 0 Output 1 1 Output Note: n: 7,6...0, pin number The alternate pin configuration is as ...

  • Page 90

    Port B Schematics ATmega103(L) 90 DDB1. When the pin is forced input, the pull-up can still be controlled by the PORTB1 bit. See the description of the SPI port for further details. • SS – Port B, ...

  • Page 91

    Figure 55. Port B Schematic Diagram (Pin PB1) Figure 56. Port B Schematic Diagram (Pin PB2) ATmega103(L) 91 ...

  • Page 92

    ATmega103(L) 92 Figure 57. Port B Schematic Diagram (Pin PB3) Figure 58. Port B Schematic Diagram (Pin PB4) MOS PULL- UP PB4 WP: WRITE PORTB WD: WRITE DDRB READ PORTB LATCH RL: RP: READ PORTB PIN RD: READ DDRB RD ...

  • Page 93

    Figure 59. Port B Schematic Diagram (Pins PB5 and PB6) MOS PULL- UP PBn WP: WRITE PORTB WD: WRITE DDRB READ PORTB LATCH RL: READ PORTB PIN RP: READ DDRB RD Figure 60. ...

  • Page 94

    Port C The Port C Data Register – PORTC Port C Schematics Port D ATmega103(L) 94 Port 8-bit output port. The Port C pins have alternate functions related to the optional external data SRAM. When using the ...

  • Page 95

    Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port D as General Digital I/O Alternate Functions of Port D 0945I–AVR–02/07 When the pins are used for the alternate ...

  • Page 96

    Port D Schematics ATmega103(L) 96 • IC1 – Port D, Bit 4 IC1, Input Capture pin for Timer/Counter1. When a positive or negative (selectable) edge is applied to this pin, the contents of Timer/Counter1 is transferred to the Timer/Counter1 Input ...

  • Page 97

    Figure 63. Port D Schematic Diagram (Pin PD4) MOS PULL- UP PD4 WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD ACIC: COMPARATOR IC ENABLE ACO: COMPARATOR OUTPUT Figure 64. Port ...

  • Page 98

    Port E ATmega103(L) 98 Figure 65. Port D Schematic Diagram (Pins PD6 and PD7) MOS PULL- UP PDn WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD ...

  • Page 99

    Port E Data Register – PORTE Port E Data Direction Register – DDRE Port E Input Pins Address – PINE Port E as General Digital I/O Alternate Functions of Port E 0945I–AVR–02/07 Bit $03 ($23) PORTE7 PORTE6 ...

  • Page 100

    Port E Schematics ATmega103(L) 100 TXD, UART Transmit Pin. • AC+ – Port E, Bit 2 AC+, Analog Comparator Positive Input. This pin is directly connected to the positive input of the analog comparator. • AC- – Port E, Bit ...

  • Page 101

    Figure 67. Port E Schematic Diagram (Pin PE1) Figure 68. Port E Schematic Diagram (Pin PE2) MOS PULL- UP PE2 WP: WRITE PORTE WD: WRITE DDRE RL: READ PORTE LATCH RP: READ PORTE PIN RD: READ DDRE ATmega103(L) RD ...

  • Page 102

    ATmega103(L) 102 Figure 69. Port E Schematic Diagram (Pin PE3) MOS PULL- UP PE3 WP: WRITE PORTE WD: WRITE DDRE RL: READ PORTE LATCH RP: READ PORTE PIN RD: READ DDRE Figure 70. Port E Schematic Diagram (Pins PE4, PE5, ...

  • Page 103

    Port F Port F Input Pins Address – PINF 0945I–AVR–02/07 Port 8-bit input port. One I/O memory location is allocated for Port F, the Port F Input Pins – PINF, $00 ($20). All Port F pins are ...

  • Page 104

    ... Default value is unprogrammed (“11”), which gives a nominal start-up time of 16 ms. The status of the Fuse bits is not affected by Chip Erase. All Atmel microcontrollers have a 3-byte signature code that identifies the device. This code can be read in both Serial and Parallel mode. The three bytes reside in a separate address space. ...

  • Page 105

    ... Table 36. Supply Voltage during Programming Part Serial Programming ATmega103 4.0 - 5.0V ATmega103L 3.2 - 3.6V This section describes how to Parallel Program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the ATmega103(L). Pulses are assumed least 500 ns unless otherwise noted. ...

  • Page 106

    ATmega103(L) 106 . Table 37. Pin Name Mapping Signal Name in Programming Mode Pin Name RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 BS2 PD7 PAGEL PA0 DATA PB7 - 0 Table 38. XA1 and XA0 ...

  • Page 107

    Enter Programming Mode Chip Erase Programming the Flash 0945I–AVR–02/07 The following algorithm puts the device in Parallel Programming mode: 1. Apply supply voltage according to Table 36, between V 2. Set RESET and BS1 pins to “0” and wait at ...

  • Page 108

    ATmega103(L) 108 E: Load Data High Byte. 1. Set BS1 to “1”. This selects high data. 2. Set XA1, XA0 to “01”. This enables data loading. 3. Set DATA = Data High Byte ($00 - $FF). 4. Give XTAL1 a ...

  • Page 109

    Programming the EEPROM 0945I–AVR–02/07 Figure 74. Programming the Flash Waveforms (Continued) DATA DATA HIGH XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 The programming algorithm for the EEPROM data memory is as follows (refer to “Pro- gramming ...

  • Page 110

    Reading the Flash Reading the EEPROM Programming the Fuse Bits ATmega103(L) 110 Figure 75. Programming the EEPROM Waveforms DATA $11 ADDR. HIGH XA1 XA2 BS1 XTAL1 WR RDY/BSY +12V RESET OE BS2 PAGEL The algorithm for reading the Flash memory ...

  • Page 111

    Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes 0945I–AVR–02/07 Bit 1 = SUT1 Fuse bit Bit 0 = SUT0 Fuse bit Bit “1”. These bits are reserved and should ...

  • Page 112

    Parallel Programming Characteristics ATmega103(L) 112 Figure 76. Parallel Programming Timing t XTAL1 XHXL t DVXH Data & Contol (DATA, XA0/1, BS1) t BVXH PAGEL t PHPL WR RDY/BSY OE DATA Table 41. Parallel Programming Characteristics T Symbol Parameter V Programming ...

  • Page 113

    Serial Downloading Serial Programming Algorithm 0945I–AVR–02/07 Both the Flash and EEPROM memory arrays can be programmed using the serial inter- face while RESET is pulled to GND, or when PEN is low during Power-on Reset. The serial interface consists of ...

  • Page 114

    Data Polling for the EEPROM ATmega103(L) 114 As an alternative to using the RESET signal, PEN can be held low during Power- on Reset while SCK is set to “0”. In this case, only the PEN value at Power-on Reset ...

  • Page 115

    Data polling is not implemented for the Flash. Table 42. Minimum Wait Delay before Writing the Next Flash or EEPROM Location Symbol 3.2V (Note WD_FLASH WD_EEPROM Note: Per page. Table 43. Read Back ...

  • Page 116

    Table 44. Serial Programming Instruction Set Instruction Byte 1 Programming Enable 1010 1100 Chip Erase 1010 1100 Read Program Memory 0010 H000 Load Program Memory Page 0100 H000 Write Program Memory Page 0100 1100 Read EEPROM Memory 1010 0000 Write ...

  • Page 117

    Figure 78. Serial Programming Waveforms SERIAL DATA INPUT MSB PE0(PDI/RXD) SERIAL DATA OUTPUT MSB PE1(PDO/TXD) SERIAL CLOCK INPUT PB1(SCK) SAMPLE ATmega103(L) LSB LSB 117 ...

  • Page 118

    Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -40°C to +105°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin except RESET with Respect to Ground ............................... -1. Voltage on RESET with Respect to Ground ...-1. ...

  • Page 119

    DC Characteristics (Continued -40°C to 85° 2.7V to 3.6V and 4.0V to 5.5V (unless otherwise noted Symbol Parameter Analog Comp V ACIO Input Offset V Analog Comp I ACLK Input Leakage A Analog Comparator ...

  • Page 120

    External Data Memory Timing Table 45. External Data Memory Characteristics, 4.0 - 6.0 Volts, No Wait State Symbol Parameter 0 1/t Oscillator Frequency CLCL 1 t ALE Pulse Width LHLL 2 t Address Valid A to ALE Low AVLL 3a ...

  • Page 121

    Table 47. External Data Memory Characteristics, 2.7 - 3.6 Volts, No Wait State Symbol Parameter 0 1/t Oscillator Frequency CLCL 1 t ALE Pulse Width LHLL 2 t Address Valid A to ALE Low AVLL 3a t Address Hold after ...

  • Page 122

    External Clock Drive Waveforms ATmega103(L) 122 Figure 79. External RAM Timing T1 0 System Clock Ø ALE 4 Address [15..8] Prev. Address Data / Address [7..0] Prev. Address 3a WR Data / Address [7..0] Prev. Address Address RD Note: Clock ...

  • Page 123

    Typical Characteristics 0945I–AVR–02/07 The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. All pins on Port F ...

  • Page 124

    ATmega103(L) 124 Figure 82. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs 2.5 3 Figure 83. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY ...

  • Page 125

    Figure 84. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs 2.5 3 Figure 85. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED 70 ...

  • Page 126

    ATmega103(L) 126 Figure 86. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 250 200 150 100 2.5 3 Figure 87. Power-save Supply Current vs. V POWER SAVE SUPPLY CURRENT vs. V WATCHDOG ...

  • Page 127

    Figure 88. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 2.5 3 Analog comparator offset voltage is measured as absolute offset. Figure 89. Analog Comparator Offset ...

  • Page 128

    ATmega103(L) 128 Figure 90. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.5 1 Common Mode Voltage (V) Figure 91. Analog Comparator Input Leakage Current ...

  • Page 129

    Figure 92. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 1400 1200 1000 800 600 400 200 0 2 2.5 3 Sink and source capabilities of I/O ports are measured on one pin at a time. ...

  • Page 130

    ATmega103(L) 130 Figure 94. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ˚ ˚ 0.5 1 Figure 95. ...

  • Page 131

    Figure 96. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ˚ ˚ ...

  • Page 132

    ATmega103(L) 132 Figure 98. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ˚ ˚ 0.5 1 ...

  • Page 133

    Figure 100. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 ATmega103( ˚ 5.0 133 ...

  • Page 134

    Register Summary Address Name Bit7 $3F ($5F) SREG I $3E ($5E) SPH SP15 $3D ($5D) SPL SP7 $3C ($5C) XDIV XDIVEN $3B ($5B) RAMPZ – $3A ($5A) EICR ISC71 $39 ($59) EIMSK INT7 $38 ($58) EIFR INTF7 $37 ($57) TIMSK ...

  • Page 135

    Instruction Set Summary Mnemonic Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers ADC Rd, Rr Add with Carry Two Registers ADIW Rdl, K Add Immediate to Word SUB Rd, Rr Subtract Two Registers SUBI Rd, K ...

  • Page 136

    Instruction Set Summary (Continued) Mnemonic Operands Description LD Rd, X Load Indirect LD Rd, X+ Load Indirect and Post-increment LD Rd, -X Load Indirect and Pre-decrement LD Rd, Y Load Indirect LD Rd, Y+ Load Indirect and Post-increment LD Rd, ...

  • Page 137

    ... Ordering Information Speed (MHz) Power Supply 4 2.7 - 3.6V 6 4.0 - 5.5V 64A 64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 0945I–AVR–02/07 Ordering Code Package ATmega103L-4AC 64A ATmega103L-4AI 64A ATmega103-6AC 64A ATmega103-6AI 64A Package Type ATmega103(L) Operation Range Commercial (0° ...

  • Page 138

    Packaging Information 64A PIN 0°~7° L Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 ...

  • Page 139

    Table of Contents 0945I–AVR–02/07 Features................................................................................................. 1 Pin Configuration .................................................................................................. 2 Description ............................................................................................ 3 Block Diagram ...................................................................................................... 4 Pin Descriptions.................................................................................................... 5 Clock Options ....................................................................................................... 6 Architectural Overview......................................................................... 8 General-purpose Register File.............................................................................. 9 ALU – Arithmetic Logic Unit................................................................................ 10 ISP Flash Program ...

  • Page 140

    ATmega103(L) ii ADC DC Characteristics ..................................................................................... 83 Interface to External SRAM................................................................ 84 I/O Ports............................................................................................... 86 Port A.................................................................................................................. 86 Port B.................................................................................................................. 87 Port C.................................................................................................................. 94 Port D.................................................................................................................. 94 Port E.................................................................................................................. 98 Port F ................................................................................................................ 103 Memory Programming...................................................................... 104 Program and Data ...

  • Page 141

    ... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...