ATMEGA103L-4AC Atmel, ATMEGA103L-4AC Datasheet - Page 57
ATMEGA103L-4AC
Manufacturer Part Number
ATMEGA103L-4AC
Description
IC MCU 128K 4MHZ A/D LV 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA103-6AC.pdf
(141 pages)
2.ATMEGA103-6AC.pdf
(4 pages)
3.ATMEGA103L-4AC.pdf
(4 pages)
Specifications of ATMEGA103L-4AC
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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EEPROM Read/Write
Access
EEPROM Address Register –
EEARH, EEARL
EEPROM Data Register –
EEDR
EEPROM Control Register –
EECR
0945I–AVR–02/07
The EEPROM Access Registers are accessible in the I/O space.
The write access time is in the range of 2.5 - 4 ms, depending on the V
self-timing function lets the user software detect when the next byte can be written. A
special EEPROM Ready interrupt can be set to trigger when the EEPROM is ready to
accept new data.
In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-
lowed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed. When it is read, the CPU is halted for four clock cycles.
The EEPROM Address Registers (EEARH and EEARL) specify the EEPROM address
in the 4 KB EEPROM space. The EEPROM Data bytes are addressed linearly between
0 and 4095.
• Bits 7..0 – EEDR7..0: EEPROM Data:
For the EEPROM write operation, the EEDR Register contains the data to be written to
the EEPROM in the address given by the EEAR Register. For the EEPROM read oper-
ation, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and will always be read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
When the I-bit in SREG and EERIE are set (one), the EEPROM Ready interrupt is
enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready interrupt
constantly generates an interrupt request when EEWE is cleared (zero).
Bit
$1F ($3F)
$1E ($3E)
Read/Write
Initial Value
Bit
$1D ($3D)
Read/Write
Initial Value
Bit
$1C ($3C)
Read/Write
Initial Value
EEAR7
R/W
MSB
R/W
15
R
–
7
0
0
R
7
0
7
–
0
EEAR6
R/W
R/W
14
R
–
6
0
0
R
6
0
6
–
0
EEAR5
R/W
R/W
13
R
–
5
0
0
R
5
0
5
–
0
EEAR4
R/W
12
R/W
R
–
4
0
0
R
4
0
4
–
0
EEAR11
EEAR3
EERIE
R/W
R/W
R/W
R/W
11
3
0
0
3
0
3
0
EEMWE
EEAR10
EEAR2
R/W
R/W
R/W
R/W
2
0
10
2
0
2
0
0
ATmega103(L)
EEAR9
EEAR1
R/W
EEWE
R/W
R/W
R/W
1
0
1
0
9
1
0
0
EEAR8
EEAR0
EERE
LSB
R/W
R/W
CC
R/W
R/W
0
0
0
0
8
0
0
0
voltages. A
EEDR
EECR
EEARH
EEARL
57
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