ATMEGA88PV-10AU Atmel, ATMEGA88PV-10AU Datasheet - Page 231

• Manufacturer Part Number: ATMEGA88PV-10AU
• Description: MCU AVR 8K ISP FLSH 10MHZ 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA88PV-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, TWI, UART
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 32TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 10MHz
• Rohs Compliant: Yes
• For Use With: ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.7.3
8025L–AVR–7/10
Slave Receiver Mode
Figure 21-14. Formats and States in the Master Receiver Mode
In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter
(see
are zero or are masked to zero.
Figure 21-15. Data transfer in Slave Receiver mode
SDA
SCL
Figure
Successfull
reception
from a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave address
Arbitration lost in slave
address or data byte
Arbitration lost and
addressed as slave
21-15). All the status codes mentioned in this section assume that the prescaler bits
From master to slave
From slave to master
$08
S
Device 1
RECEIVER
SLAVE
SLA
TRANSMITTER
R
Device 2
MASTER
MR
A or A
DATA
$40
$48
$38
$68
A
A
A
$78
Other master
Other master
n
continues
continues
P
$B0
Device 3
DATA
A
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
........
ATmega48P/88P/168P
$50
$38
To corresponding
states in slave mode
A
A
Other master
DATA
continues
Device n
$58
A
V
CC
$10
P
R
S
R1
SLA
R2
W
R
MT
231