ATMEGA88PV-10AU Atmel, ATMEGA88PV-10AU Datasheet - Page 56

• Manufacturer Part Number: ATMEGA88PV-10AU
• Description: MCU AVR 8K ISP FLSH 10MHZ 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA88PV-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, TWI, UART
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 32TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 10MHz
• Rohs Compliant: Yes
• For Use With: ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8025L–AVR–7/10
WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for
keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System
Reset Mode, WDIE must be set after each interrupt. This should however not be done within the
interrupt service routine itself, as this might compromise the safety-function of the Watchdog
System Reset mode. If the interrupt is not executed before the next time-out, a System Reset
will be applied.
Table 10-1.
Note:
• Bit 4 – WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,
and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 – WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-
ditions causing failure, and a safe start-up after the failure.
• Bit 5, 2:0 – WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-
ning. The different prescaling values and their corresponding time-out periods are shown in
Table 10-2 on page
Table 10-2.
WDTON
WDP3
0
0
0
0
0
0
0
0
1
1
1
1
0
1. WDTON Fuse set to “0” means programmed and “1” means unprogrammed.
(1)
WDP2
0
0
0
0
1
1
1
1
Watchdog Timer Configuration
Watchdog Timer Prescale Select
WDE
0
0
1
1
x
56.
WDP1
0
0
1
1
0
0
1
1
WDIE
WDP0
0
1
0
1
x
0
1
0
1
0
1
0
1
Mode
Stopped
Interrupt Mode
System Reset Mode
Interrupt and System Reset
Mode
System Reset Mode
Number of WDT Oscillator
128K (131072) cycles
256K (262144) cycles
16K (16384) cycles
32K (32768) cycles
64K (65536) cycles
2K (2048) cycles
4K (4096) cycles
8K (8192) cycles
Cycles
ATmega48P/88P/168P
Action on Time-out
None
Interrupt
Reset
Interrupt, then go to System
Reset Mode
Reset
Typical Time-out at
V
CC
0.125 s
16 ms
32 ms
64 ms
0.25 s
0.5 s
1.0 s
2.0 s
= 5.0V
56