IC MCU OTP 8BIT 1K 20DIP

COP8SAA720N9

Manufacturer Part NumberCOP8SAA720N9
DescriptionIC MCU OTP 8BIT 1K 20DIP
ManufacturerNational Semiconductor
SeriesCOP8™ 8SA
COP8SAA720N9 datasheet
 


Specifications of COP8SAA720N9

Core ProcessorCOP8Core Size8-Bit
Speed10MHzConnectivityMicrowire/Plus (SPI)
PeripheralsPOR, PWM, WDTNumber Of I /o16
Program Memory Size1KB (1K x 8)Program Memory TypeOTP
Ram Size64 x 8Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 V
Oscillator TypeInternalOperating Temperature0°C ~ 70°C
Package / Case20-DIP (0.300", 7.62mm)Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Eeprom Size-Data Converters-
Other names*COP8SAA720N9
COP8SAA720N9B
COP8SAA720NB
  
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Page 11/60

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AC Electrical Characteristics
−40˚C
T
+85˚C unless otherwise specified.
A
Parameter
Inputs
t
SETUP
t
HOLD
Output Propagation Delay (Note 16)
t
, t
PD1
PD0
SO, SK
All Others
MICROWIRE Setup Time (t
) (Note 16)
UWS
MICROWIRE Hold Time (t
) (Note 16)
UWH
MICROWIRE Output Propagation Delay (t
MICROWIRE Maximum Shift Clock
Master Mode
Slave Mode
Input Pulse Width (Note 17)
Interrupt Input High Time
Interrupt Input Low Time
Timer 1 Input High Time
Timer 1 Input Low Time
Reset Pulse Width
Note 11: t
= Instruction cycle time (Clock input frequency divided by 10).
C
Note 12: Maximum rate of voltage change must be
Note 13: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V
and outputs driven low but not connected to a load.
Note 14: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal
or external configuration, CKI is TRI-STATE. Measurement of I
programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V
to HALT mode entered via setting bit 7 of the G Port data register.
Note 15: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
>
biased at voltages
V
(the pins do not have source current when biased at a voltage below V
CC
pins will not latch up. The voltage at the pins must be limited to
ESD transients.
Note 16: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 17: Parameter characterized but not tested.
Note 18: Rise times faster than this specification may reset the device if POR is enabled and may affect the value of Idle Timer T0 if POR is not enabled.
(Continued)
Conditions
4.5V
V
5.5V
CC
<
2.7V
V
4.5V
CC
4.5V
V
5.5V
CC
<
2.7V
V
4.5V
CC
R
= 2.2k, C
= 100 pF
L
L
4.5V
V
5.5V
CC
<
2.7V
V
4.5V
CC
4.5V
V
5.5V
CC
<
2.7V
V
4.5V
CC
)
UPD
<
0.5 V/ms.
HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2–G5
DD
). The effective resistance to V
CC
<
14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes
FIGURE 4. MICROWIRE/PLUS Timing
11
Min
Typ
Max
200
500
60
150
0.7
1.75
1.0
2.5
20
56
220
500
1
1
1
1
1
1
; clock monitor disabled. Parameter refers
CC
>
V
and the pins will have sink current to V
CC
is 750
(typical). These two
CC
DS012838-9
www.national.com
Units
ns
ns
ns
ns
µs
µs
µs
µs
ns
ns
ns
kHz
MHz
t
C
t
C
t
C
t
C
µs
CC
when
CC