MC9328MXLVM20R2 Freescale Semiconductor, MC9328MXLVM20R2 Datasheet

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... Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2004, 2005, 2006. All rights reserved. Document Number: MC9328MXL Rev. 8, 12/2006 MC9328MXL Package Information ...

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... Controller DMAC Bus AIPI 2 (11 Chnl) Control EIM & SDRAMC Figure 1. i.MXL Functional Block Diagram MC9328MXL Technical Data, Rev. 8 Standard System I/O GPIO PWM Timer 1 & 2 RTC Watchdog Multimedia Multimedia Accelerator Video Port Human Interface LCD Controller 2 S) Module Freescale Semiconductor ...

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... Logic level zero is a voltage that corresponds to Boolean false (0) state. • To set a bit or bits means to establish logic level one. • To clear a bit or bits means to establish logic level zero. • A signal is an electronic construct whose state conveys or changes in state convey information. Freescale Semiconductor Table 1. i.MXL Ordering Information Temperature Solderball Type ...

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... DTACK as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 clock counts have elapsed. 4 Table 2. i.MXL Signal Descriptions Function/Notes External Bus/Chip-Select (EIM) MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor ...

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... Power-on reset, External reset (RESET_IN), and Watchdog time-out. POR Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally generated by an external RC circuit designed to detect a power-up event. Freescale Semiconductor Function/Notes Bootstrap SDRAM Controller Clocks and Resets MC9328MXL Technical Data, Rev ...

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... This signal is used to control the LCD bias voltage as contrast control. SPL_SPR Program horizontal scan direction (Sharp panel dedicated signal). PS Control signal output for source driver (Sharp panel dedicated signal). 6 Function/Notes JTAG DMA ETM CMOS Sensor Interface LCD Controller MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor ...

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... SD_CMD SD Command—If the system designer does not wish to make use of the internal pull-up, via the Pull-up enable register, a 4.7K–69K external pull up resistor must be added. SD_CLK MMC Output Clock Freescale Semiconductor Function/Notes SPI 1 and SPI 2 General Purpose Timers USB Device Secure Digital Interface MC9328MXL Technical Data, Rev ...

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... Transmit Data SSI_RXDAT Receive Data SSI_TXCLK Transmit Serial Clock SSI_RXCLK Receive Serial Clock SSI_TXFS Transmit Frame Sync SSI_RXFS Receive Frame Sync 2 I2C_SCL I C Clock 2 I2C_SDA I C Data 8 Function/Notes Memory Stick Interface UARTs – IrDA/Auto-Bauding 2 S protocol MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor ...

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... NVDD1 E4 D3 D29 NVDD1 E1 E2 A21 NVDD1 F3 E3 D28 Freescale Semiconductor Function/Notes PWM Test Function ® registered trademark of National Semiconductor.) Digital Supply Pins Supply Pins – Analog Modules Internal Power Supply Table 6 allows the user to select the function of each pin by Primary ...

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... A7 O I/O 69K A6 O I/O 69K A5 O I/O 69K A4 O I/O 69K MC9328MXL Technical Data, Rev. 8 GPIO AIN BIN AOUT Pull Mux -Up PA28 69K PA27 69K PA26 69K PA25 69K PA24 69K Freescale Semiconductor Default A20 A19 A18 A17 A16 ...

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... NVDD1 M9 R8 BCLK NVDD1 L8 P7 NVDD1 N9 N7 PA17 NVDD1 K10 N8 NVDD1 M10 M7 RW NVDD1 P10 T8 MA11 NVDD1 P9 M8 MA10 NVDD1 N10 R9 NVDD1 R12 P9 DQM3 Freescale Semiconductor Primary Alternate Pull- Dir Signal Dir Up O I/O 69K I/O 69K I/O 69K I/O 69K O ...

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... NVDD2 J11 P14 I2C_SCL NVDD2 H14 P15 I2C_SDA 12 Primary Alternate Pull- Dir Signal Dir Static Static I 69K 69K 69K I 69K I 69K O I/O MC9328MXL Technical Data, Rev. 8 GPIO AIN BIN AOUT Pull Mux -Up PA16 69K PA15 69K Freescale Semiconductor Default PA16 PA15 ...

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... LD7 NVDD2 B14 J11 LD6 NVDD2 A15 H14 LD5 NVDD2 A14 H13 LD4 NVDD2 B13 H16 LD3 NVDD2 A13 H12 LD2 NVDD2 D12 G16 LD1 NVDD2 B12 H11 LD0 NVDD2 C11 G15 FLM/VSY Freescale Semiconductor Primary Alternate Pull- Dir Signal Dir ...

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... PC11 69K PC10 69K PC9 69K PC8 69K PC7 69K PC6 69K PC5 69K PC4 69K PC3 69K PB31 69K Freescale Semiconductor Default PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PC17 PC16 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 ...

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... SD_CLK NVDD4 B1 A2 SD_DAT3 NVDD4 C5 E5 SD_DAT2 NVDD4 D3 B2 SD_DAT1 NVDD4 C2 C3 SD_DAT0 NVDD1 D5 K8 NVDD1 G6 A1 NVSS NVDD1 E5 H5 NVDD1 H6 T1 NVSS QVDD1 J8 H9 QVDD1 E6 H8 QVSS Freescale Semiconductor Primary Alternate Pull- Dir Signal Dir I I/O I I/O MS_BS O MS_SCLK O I/O ...

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... Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static MC9328MXL Technical Data, Rev. 8 GPIO AIN BIN AOUT Default Pull -Up Freescale Semiconductor ...

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... Because AVDD pins are supply voltages to the analog pads recommended to isolate and noise-filter the AVDD pins from other VDD pins. For more information about I/O pads grouping per VDD, please refer to Freescale Semiconductor Table 4. Maximum Ratings Rating MC9328MXL Technical Data, Rev. 8 ...

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... Min Typical Max – QVDD at – 1.8V = 120mA; NVDD+AVDD at 3.0V = 30mA – 25 – – 45 – – 35 – – 60 – Freescale Semiconductor Unit °C °C ° Unit mA μA μA μA μA ...

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... Parameter EXTAL32k input jitter (peak to peak) EXTAL32k startup time EXTAL16M input jitter (peak to peak) 1 EXTAL16M startup time 1 The 16 MHz oscillator is not recommended for use in new designs. Freescale Semiconductor Parameter = 2.0 mA) = -2.5 mA under an operating temperature from T DD min DD max Table 7. Tristate Signal Timing Parameter Table 8 ...

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... Figure 2. Trace Port Timing Diagram 1.8 ± 0.1 V Minimum Maximum 0 85 1.3 – 3 – – 4 – 3 MC9328MXL Technical Data, Rev. 8 for the ETM9 timing parameters used 1 Valid Data 4b 3.0 ± 0.3 V Unit Minimum Maximum 0 100 MHz 2 – – ns – – Freescale Semiconductor ...

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... Freq jitter (p-p) – Phase jitter (p-p) Integer MF, FPL mode, Vcc=1.8V Power supply voltage – Power dissipation FOL mode, integer MF, f dck Freescale Semiconductor 1.8 ± 0.1 V Minimum Maximum 2.28 – 3.42 – Table 10. In this table, T ref Table 10 ...

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... RESET_DRAM HRESET RESET_OUT CLK32 HCLK RESET_IN HRESET RESET_OUT 6 CLK32 HCLK Figure 4. Timing Relationship with RESET_IN 22 NOTE 1 10% AVDD 2 Exact 300ms Figure 3. Timing Relationship with POR 5 MC9328MXL Technical Data, Rev. 8 Figure 3 and 3 7 cycles @ CLK32 4 14 cycles @ CLK32 14 cycles @ CLK32 4 Freescale Semiconductor ...

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... External Interface Module The External Interface Module (EIM) handles the interface to devices external to the i.MXL processor, including the generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in Figure 5, and Freescale Semiconductor 1.8 ± 0.1 V Min 1 note 300 ...

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... MC9328MXL Technical Data, Rev 10a 3.0 ± 0.3 V Unit Max Min Typical Max 9.11 2.4 3.2 8.8 ns 5.69 1.5 2.4 5.5 ns 7.87 2.6 3.2 7.6 ns 6.31 1.5 2.4 6.1 ns 6.52 1.3 2.7 6.3 ns 6.11 1.8 2.5 5.9 ns Freescale Semiconductor ...

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... DTACK Signal Timing Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units of measure for this figure are found in the associated tables. Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Min Typical 2.32 2.62 6 ...

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... The external wait input requirement is eliminated when CS5 is programmed to use internal wait state Figure 6. WAIT Read Cycle without DMA Minimum See note 2 56.81 2T+1.57 T-1.49 1.5T-0.68 0.06 MC9328MXL Technical Data, Rev 3.0 ± 0.3 V Maximum – 3T – 57.28 – 1020T 3T+7.33 – 1.5T-0.06 0.18 0 1019T 1T 1020T Freescale Semiconductor Unit ...

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... Wait asserted to OE negated 7 Data hold timing after OE negated 8 Data ready after wait is asserted 9 CS deactive to next CS active 10 OE negate after EB negate 11 Wait becomes low after CS5 asserted Freescale Semiconductor Minimum See note 2 1.5T-0.68 2T+1.57 T-1.49 MC9328MXL Technical Data, Rev. 8 Functional Description and Application Information ...

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... Wait asserted after CS5 asserted 28 Minimum Figure 8. WAIT Write Cycle without DMA Minimum See note 2 See note 2 3T 2.5T-3.63 64.22 – MC9328MXL Technical Data, Rev. 8 3.0 ± 0.3 V Maximum 1T 1020T 3.0 ± 0.3 V Maximum – – – 2.5T-1.16 – 1020T Freescale Semiconductor Unit ns Unit ...

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... WAIT Write Cycle DMA Enabled Address 1 programmable min 0ns CS5 2 programmable min 0ns (logic high) WAIT 9 DATABUS Freescale Semiconductor Minimum T+2.66 2T+0.03 – 0. Figure 9. WAIT Write Cycle DMA Enabled MC9328MXL Technical Data, Rev. 8 Functional Description and Application Information 3.0 ± 0.3 V Maximum 2T+7 ...

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... Minimum See note 2 See note 2 3T 2.5T-3.63 – – T+2.66 2T+0.03 – MC9328MXL Technical Data, Rev. 8 3.0 ± 0.3 V Unit Maximum – – – 2.5T-1.16 0.09 1020T 2T+7.96 – T – 0.5T+0.5 1019T 1020T , including i.MXL Freescale Semiconductor ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Freescale Semiconductor Seq/Nonseq Read V1 Last Valid Data Last Valid Address Read Figure 10. WSC = 1, A.HALF/E.HALF MC9328MXL Technical Data, Rev. 8 Functional Description and Application Information ...

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... Last Valid Data weim_hrdata weim_hready BCLK (burst clock) Last Valid Address ADDR CS0 R/W LBA OE EB DATA Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF 32 Nonseq Write V1 Write Data (V1) Last Valid Data Last Valid Data MC9328MXL Technical Data, Rev. 8 Unknown V1 Write Write Data (V1) Freescale Semiconductor ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF Freescale Semiconductor Read V1 Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Technical Data, Rev. 8 Functional Description and Application Information ...

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... Last Valid Data weim_hrdata weim_hready BCLK (burst clock) ADDR Last Valid Addr CS0 R/W LBA OE EB DATA Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF 34 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Technical Data, Rev. 8 Address 2/2 Half Word Freescale Semiconductor ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Technical Data, Rev Word ...

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... BCLK (burst clock) ADDR Last Valid Addr CS3 R/W LBA OE EB DATA Last Valid Data Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF 36 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Technical Data, Rev. 8 Address 2/2 Half Word Freescale Semiconductor ...

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... EBx (EBC =1) weim_data_in Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Technical Data, Rev Word ...

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... BCLK (burst clock) ADDR Last Valid Addr CS2 R/W LBA OE EB DATA Last Valid Data Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF 38 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Technical Data, Rev. 8 Address 2/2 Half Word Freescale Semiconductor ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Technical Data, Rev Word ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF 40 Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... Last Valid Addr CS2 R/W LBA OE EB DATA Last Valid Data Figure 20. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Technical Data, Rev. 8 Unknown Address ...

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... BCLK (burst clock) ADDR Last Valid Addr CS2 R/W LBA OE EB DATA Last Valid Data Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF 42 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Technical Data, Rev. 8 Unknown Address 2/2 Half Word Freescale Semiconductor ...

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... EBx (EBC =1) DATA DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF Freescale Semiconductor Nonseq Write V8 Last Valid Data Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MXL Technical Data, Rev ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF 44 Read Idle Nonseq Write V8 Last Valid Data Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MXL Technical Data, Rev. 8 Write Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... Last Valid Addr CS R/W LBA OE EB DATA Last Valid Data Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Write Data (Word) Last Valid Data Address V1 Write Write Data (1/2 Half Word) MC9328MXL Technical Data, Rev. 8 Address Write Data (2/2 Half Word) ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF 46 Nonseq Write V8 Last Valid Data Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MXL Technical Data, Rev. 8 Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF Freescale Semiconductor Functional Description and Application Information Idle Seq Read V2 Read Data (V1) Address V1 CNC Read Read Data (V1) MC9328MXL Technical Data, Rev ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF 48 Idle Nonseq Write V8 Last Valid Data Address V1 CNC Read Read Data Last Valid Data MC9328MXL Technical Data, Rev. 8 Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... EBx (EBC =1) ECB DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF Freescale Semiconductor Functional Description and Application Information Nonse Read V5 Address V1 Read V1 Word V2 Word MC9328MXL Technical Data, Rev. 8 Idle ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 29. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD 50 Seq Seq Read Read Word V2 Word Address V1 Read V1 Word V2 Word MC9328MXL Technical Data, Rev. 8 Idle Seq Read V4 V3 Word V4 Word V3 Word V4 Word Freescale Semiconductor ...

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... EBx (EBC =1) ECB DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Seq Read V2 V1 Word Address V1 Read V1 1/2 V1 2/2 MC9328MXL Technical Data, Rev. 8 ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF 52 Last Valid Data Address V1 Read V1 1/2 MC9328MXL Technical Data, Rev. 8 Idle Seq Read V2 V1 Word V2 Word V1 2/2 V2 1/2 V2 2/2 Freescale Semiconductor ...

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... ECB DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Last Valid Data Address V1 Read V1 1/2 MC9328MXL Technical Data, Rev. 8 ...

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... Figure 33. Non-TFT Panel Timing Table 17. Non TFT Panel Timing Diagram Allowed Register 1, 2 Minimum Value – 0 through Figure 38 show the timing relationship of the master SPI using MC9328MXL Technical Data, Rev Actual Value Unit HWAIT2+2 4 Tpix HWIDTH+1 Tpix 0 ≤ T3 ≤ – HWAIT1+1 Tpix Freescale Semiconductor ...

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... Figure 36. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger SS (input) SCLK, MOSI, MISO Figure 37. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT SS (input) 6 SCLK, MOSI, MISO Figure 38. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge Freescale Semiconductor Functional Description and Application Information MC9328MXL Technical Data, Rev. 8 ...

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... Figure 39. SPI SCLK Timing Diagram Parameter Minimum 1 Figure 40. SCLK to LD Timing Diagram MC9328MXL Technical Data, Rev. 8 through Figure 38 3.0 ± 0.3 V Unit Maximum 1 – – • Tsclk – – – – – ns 3.0 ± 0.3 V Unit Maximum 0 10 MHz 100 – ns Freescale Semiconductor ...

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... Symbol Description T1 End beginning of VSYN T2 HSYN period T3 VSYN pulse width T4 End of VSYN to beginning HSYN pulse width T6 End of HSYN to beginning End beginning of HSYN Freescale Semiconductor Functional Description and Application Information 3.0 ± 0.3 V Minimum – Non-display XMAX T8 (1,1) (1,2) T9 T10 Minimum T5+T6 ...

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... MMC/SD module (inner system) and the application (user programming). Bus Clock CMD_DAT Input CMD_DAT Output Figure 42. Chip-Select Read Cycle Timing Diagram 58 Minimum - Valid Data 7 Valid Data 6a MC9328MXL Technical Data, Rev. 8 Corresponding Register Value Unit Figure 41, all 3 signals Valid Data Valid Data 6b Freescale Semiconductor ...

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... NCR clock cycles as illustrated in Figure 47 are defined in Table 23. Table 23. State Signal Parameters for Card Active Symbol Z High impedance state D * CRC Cyclic redundancy check bits (7 bits) Freescale Semiconductor 1.8 ± 0.1 V Minimum Maximum 0 25 400 6/33 15/75 – 10/50 (5.00) – ...

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... CRC Timing of command sequences (all modes) until the card sees a stop transmission command. The AC MC9328MXL Technical Data, Rev. 8 CID/OCR Content Identification Timing CID/OCR Content SET_RCA Timing and Response Content CRC Host Command Content CRC Host Command Content CRC beginning AC Freescale Semiconductor ...

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... The card sends back the CRC check result status token on the data line. If there was a transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC status (010) is returned. The card expects a continuous flow of data blocks configured to multiple block mode, with the flow terminated by a stop transmission command. Freescale Semiconductor N cycles CR ...

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... Functional Description and Application Information The stop transmission command may occur when the card is in different states. different scenarios on the bus. 62 Figure 46. Timing Diagrams at Data Write MC9328MXL Technical Data, Rev. 8 Figure 47 shows the Freescale Semiconductor ...

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... Figure 47. Stop Transmission During Different Scenarios Table 24. Timing Values for Parameter MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL) Command response cycle Identification response cycle Access time delay cycle Freescale Semiconductor Functional Description and Application Information Figure 43 through Symbol Minimum NCR ...

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... Symbol Minimum NRC 8 NCC 8 NWR 2 NST 2 Response Block Data Interrupt Period Figure 48. SDIO IRQ Timing Diagram MC9328MXL Technical Data, Rev. 8 Figure 47 (Continued) Maximum Unit – Clock cycles – Clock cycles – Clock cycles 2 Clock cycles ****** IRQ S Block Data E Freescale Semiconductor IRQ ...

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... The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0 and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO. Freescale Semiconductor CMD52 CRC ...

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... MS_SCLKO rise time 1 10 MS_SCLKO fall time 1 11 MS_BS delay time Figure 50. MSHC Signal Timing Diagram Parameter 1 1 MC9328MXL Technical Data, Rev 3.0 ± 0.3 V Unit Minimum Maximum – 25 MHz 20 – – ns – – – 25 MHz 20 – – ns – – – Freescale Semiconductor ...

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... PWM Output Table 26. PWM Output Timing Parameter Table Ref No. Parameter 1 System CLK frequency 1 2a Clock high time 1 2b Clock low time 1 3a Clock fall time Freescale Semiconductor Parameter 1,2 Table 26 Figure 51. PWM Output Timing Diagram 1.8 ± 0.1 V Minimum Maximum 3.3 – ...

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... Figure 52. SDRAM Read Cycle Timing Diagram 68 1.8 ± 0.1 V Minimum Maximum – 6.67 5.7 – 5.7 – COL/ Data Note: CKE is high during the read/write cycle. MC9328MXL Technical Data, Rev. 8 3.0 ± 0.3 V Unit Minimum Maximum – 5/ – – Freescale Semiconductor ...

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... Data out high-impedance time ( Data out high-impedance time ( Active to read/write command period ( SDRAM clock cycle time. This settings can be found in the MC9328MXL reference manual. RCD Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Minimum Maximum 2.67 6 11.4 3.42 2.28 3 ...

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... Maximum 2.67 6 11.4 3.42 2. RCD2 4.0 2.28 MC9328MXL Technical Data, Rev COL/ DATA 3.0 ± 0.3 V Minimum Maximum – 4 – – 4 – – 10 – – 3 – – 2 – – t – RP2 – t – RCD2 – 2 – – 2 – Freescale Semiconductor Unit ...

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... Address setup time 5 Address hold time 6 Precharge cycle period 7 Auto precharge command period 1 t and t = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference manual Freescale Semiconductor Figure 54. SDRAM Refresh Timing Diagram 1.8 ± 0.1 V Minimum Maximum 2.67 6 11.4 3 ...

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... Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved in the form of packets, however, because isochronous pipes are given a fixed portion of the USB bandwidth at all times, there is no end-of-transfer. 72 MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor ...

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... ROE_VMO USBD_VPO high to USBD_ROE deactivated VPO_ROE USBD_VMO low to USBD_ROE deactivated (includes SE0) VMO_ROE SE0 interval of EOP FEOPT Data transfer rate PERIOD Freescale Semiconductor 6 t PERIOD 2 Parameter MC9328MXL Technical Data, Rev. 8 Functional Description and Application Information t 4 VMO_ROE 3 t VPO_ROE t FEOPT 5 3.0 ± 0.3 V ...

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... The I C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. SDA SCL 74 Parameter Figure 58. Definition of Bus Timing for I MC9328MXL Technical Data, Rev FEOPR 3.0 ± 0.3 V Unit Minimum Maximum 82 – Freescale Semiconductor ...

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... STCK Output STFS (bl) Output STFS (wl) Output STXD Output SRXD Input Note: SRXD input in synchronous mode only. Figure 59. SSI Transmitter Internal Clock Timing Diagram Freescale Semiconductor 2 Table 32 Bus Timing Parameter Table 1.8 ± 0.1 V Minimum Maximum 182 0 11 ...

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... SRFS (bl) Output SRFS (wl) Output SRXD Input Figure 60. SSI Receiver Internal Clock Timing Diagram STCK Input STFS (bl) Input STFS (wl) Input STXD Output SRXD Input Note: SRXD Input in Synchronous mode only Figure 61. SSI Transmitter External Clock Timing Diagram MC9328MXL Technical Data, Rev Freescale Semiconductor ...

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... STCK high to STXD high impedance 13 SRXD setup time before SRCK low 14 SRXD hold time after SRCK low External Clock Operation (Port C Primary Function 15 STCK/SRCK clock period 16 STCK/SRCK clock high period 17 STCK/SRCK clock low period Freescale Semiconductor 1.8 ± 0.1 V Minimum 1 (Port C Primary Function ...

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... Freescale Semiconductor Unit ...

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... STCK high to STFS (wl) low 3 25 SRCK high to SRFS (wl) low 26 STCK high to STXD valid from high impedance 27a STCK high to STXD high 27b STCK high to STXD low Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Minimum Maximum 1 (Port B Alternate Function 95 – ...

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... Maximum 17.90 29.75 1.14 – 0 – 18.81 – 0 – 1.14 – 0 – Figure 64 MC9328MXL Technical Data, Rev. 8 3.0 ± 0.3 V Unit Minimum Maximum 15.7 26.1 ns 1.0 – – 16.5 – – 1.0 – – ns shows the timing diagram Table 35. Freescale Semiconductor ...

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... Table 35. Gated Clock Mode Timing Parameters Ref No. 1 csi_vsync to csi_hsync 2 csi_hsync to csi_pixclk 3 csi_d setup time 4 csi_d hold time 5 csi_pixclk high time 6 csi_pixclk low time 7 csi_pixclk frequency Freescale Semiconductor Functional Description and Application Information 5 2 Valid Data Valid Data Valid Data Valid Data 3 4 Parameter Min ...

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... The parameters for the timing diagrams are listed in VSYNC PIXCLK DATA[7:0] Figure 65. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge 82 1 Valid Data Valid Data 2 3 MC9328MXL Technical Data, Rev. 8 Figure 66 shows the timing diagram Table 36 Valid Data Freescale Semiconductor ...

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... Falling-edge latch data max fall time allowed = (negative duty cycle - hold time) max rise time allowed = (positive duty cycle - setup time) Freescale Semiconductor Functional Description and Application Information 1 Valid Data Valid Data ...

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Pin-Out and Package Information Table 37 illustrates the package pin assignments for the 256-pin MAPBGA package. For a complete listing of signals, see the Signal Multiplexing Table 3 on page USBD_ A NVSS ...

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Table 38 illustrates the package pin assignments for the 225-contact MAPBGA package. For a complete listing of signals, see the Signal Multiplexing Table 3 on page USBD_ USBD_ A SD_CMD PB15 PB19 ROE SUSPND USBD_ ...

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... DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994. 3.MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. Figure 67. i.MXL 256 MAPBGA Mechanical Drawing 86 Case Outline 1367 MC9328MXL Technical Data, Rev. 8 SIDE VIEW Freescale Semiconductor ...

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... DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. 5.PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE Figure 68. i.MXL 225 MAPBGA Mechanical Drawing Freescale Semiconductor Case Outline 1304B MC9328MXL Technical Data, Rev. 8 Pin-Out and Package Information SIDE VIEW ...

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... MC9328MXL Product Brief (order number MC9328MXLP) MC9328MXL Reference Manual (order number MC9328MXLRM) The Freescale manuals are available on the Freescale Semiconductors Web site at http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www ...

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... Freescale Semiconductor NOTES MC9328MXL Technical Data, Rev ...

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... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...