MC9328MXLVM20R2 Freescale Semiconductor, MC9328MXLVM20R2 Datasheet - Page 28

• Manufacturer Part Number: MC9328MXLVM20R2
• Description: IC MCU I.MX 200MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MXLr

Specifications of MC9328MXLVM20R2

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, I²C, Memory Stick, MMC/SD, SPI, SSI, UART/USART, USB
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Functional Description and Application Information
Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
4.4.2.3
28
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
Number
Number
12
1
2
3
4
5
6
from i.MXL
OE
Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Address
DATABUS
(logic high)
Wait pulse width
CS5 assertion time
EB assertion time
CS5 pulse width
RW negated before CS5 is negated
RW negated to Address inactive
Wait asserted after CS5 asserted
WAIT Write Cycle without DMA
CS5
RW
EB
WAIT
1
2
9
Characteristic
Characteristic
programmable
min 0ns
programmable
min 0ns
Figure 8. WAIT Write Cycle without DMA
11
MC9328MXL Technical Data, Rev. 8
6
3
12
See note 2
See note 2
Minimum
2.5T-3.63
64.22
3T
–
Minimum
1T
7
3.0 ± 0.3 V
3.0 ± 0.3 V
8
4
10
Maximum
2.5T-1.16
Maximum
1020T
5
Freescale Semiconductor
1020T
–
–
–
–
Unit
Unit
ns
ns
ns
ns
ns
ns
ns