MC9328MXLVM20R2 Freescale Semiconductor, MC9328MXLVM20R2 Datasheet - Page 80

• Manufacturer Part Number: MC9328MXLVM20R2
• Description: IC MCU I.MX 200MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MXLr

Specifications of MC9328MXLVM20R2

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, I²C, Memory Stick, MMC/SD, SPI, SSI, UART/USART, USB
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

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3
Functional Description and Application Information
4.14
The CMOS Sensor Interface (CSI) module consists of a control register to configure the interface timing,
a control register for statistic data generation, a status register, interface logic, a 32 × 32 image data receive
FIFO, and a 16 × 32 statistic data FIFO.
4.14.1
Figure 63
and the CSI is programmed to received data on the positive edge.
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in
80
Ref
No.
28
29
30
31
32
33
34
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B
alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary
function and Port B alternate function. When SSI signals are configured as inputs, the SSI module selects the input based on
FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function.
bl = bit length; wl = word length.
STCK high to STXD high impedance
SRXD setup time before SRCK low
SRXD hold time after SRCK low
SRXD setup before STCK falling
SRXD hold after STCK falling
SRXD setup before STCK falling
SRXD hold after STCK falling
CMOS Sensor Interface
shows the timing diagram when the CMOS sensor output data is configured for negative edge
Gated Clock Mode
Table 34. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
Synchronous External Clock Operation (Port B Alternate Function
Parameter
Synchronous Internal Clock Operation (Port B Alternate Function
MC9328MXL Technical Data, Rev. 8
Minimum
17.90
18.81
1.14
1.14
0
0
0
1.8 ± 0.1 V
Maximum
29.75
Figure 64
–
–
–
–
–
–
Table
Minimum
shows the timing diagram
15.7
16.5
1.0
1.0
0
0
0
2
35.
2
3.0 ± 0.3 V
)
)
Freescale Semiconductor
Maximum
26.1
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns