MC9328MXLVM20R2 Freescale Semiconductor, MC9328MXLVM20R2 Datasheet - Page 54

• Manufacturer Part Number: MC9328MXLVM20R2
• Description: IC MCU I.MX 200MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MXLr

Specifications of MC9328MXLVM20R2

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, I²C, Memory Stick, MMC/SD, SPI, SSI, UART/USART, USB
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Functional Description and Application Information
4.4.4
4.5
To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as a
master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY
signal (input). The SPI1 Sample Period Control Register (PERIODREG1) and the SPI2 Sample Period
Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either SPI 1 or
SPI 2. When the SPI 1 module is configured as a slave, the user can configure the SPI1 Control Register
(CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS becomes an input
signal, and is used to latch data into or load data out to the internal data shift registers, as well as to
increment the data FIFO.
different triggering mechanisms.
54
LD[15:0]
1
2
3
4
5
Symbol
SPI Timing Diagrams
HSYN
Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register.
Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong.
VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all
these 3 signals are active high.
Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1).
Ts is the shift clock period. Ts = Tpix * (panel data bus width).
VSYN
SCLK
Non-TFT Panel Timing
T1
T2
T3
T4
HSYN to VSYN delay
HSYN pulse width
VSYN to SCLK
SCLK to HSYN
Figure 34
Parameter
T2
Table 17. Non TFT Panel Timing Diagram
through
Figure 33. Non-TFT Panel Timing
3
MC9328MXL Technical Data, Rev. 8
T1
Figure 38
T3
Minimum Value
Allowed Register
show the timing relationship of the master SPI using
0
0
–
0
XMAX
1, 2
Ts
Actual Value
0 ≤ T3 ≤ Ts
HWIDTH+1
HWAIT2+2
HWAIT1+1
T4
Freescale Semiconductor
5
T2
Tpix
Unit
Tpix
Tpix
–
T1
4