MC9328MXLVM20R2 Freescale Semiconductor, MC9328MXLVM20R2 Datasheet - Page 29

• Manufacturer Part Number: MC9328MXLVM20R2
• Description: IC MCU I.MX 200MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MXLr

Specifications of MC9328MXLVM20R2

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, I²C, Memory Stick, MMC/SD, SPI, SSI, UART/USART, USB
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

4.4.2.4
Freescale Semiconductor
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmable by WEA bits in CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
Number
Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
10
11
12
7
8
9
OE
DATABUS
Address
Wait asserted to RW negated
Data hold timing after RW negated
Data ready after CS5 is asserted
EB negated after CS5 is negated
Wait becomes low after CS5 asserted
Wait pulse width
(logic high)
WAIT Write Cycle DMA Enabled
WAIT
CS5
RW
EB
1
2
Characteristic
programmable
min 0ns
programmable
9
min 0ns
12
Figure 9. WAIT Write Cycle DMA Enabled
MC9328MXL Technical Data, Rev. 8
6
3
13
Minimum
2T+0.03
T+2.66
0.5T
1T
–
0
Functional Description and Application Information
7
3.0 ± 0.3 V
8
4
5
Maximum
0.5T+0.5
2T+7.96
11
1019T
1020T
10
–
T
Unit
ns
ns
ns
ns
ns
ns
29