MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 129

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
12–11
9–8
3–0
Bit
15
14
13
10
7
6
5
4
Name
MAP
EMU
DDC
SSM
TRC
UHE
BTB
NPL
IPI
—
—
Force processor references in emulator mode.
0 All emulator-mode references are mapped into supervisor code and data spaces.
1 The processor maps all references while in emulator mode to a special address space, TT = 10,
Force emulation mode on trace exception. If TRC = 1, the processor enters emulator mode when a trace
exception occurs. If TRC=0, the processor enters supervisor mode.
Force emulation mode. If EMU = 1, the processor begins executing in emulator mode. See
“Emulator
Debug data control. Controls operand data capture for DDATA, which displays the number of bytes defined
by the operand reference size before the actual data; byte displays 8 bits, word displays 16 bits, and long
displays 32 bits (one nibble at a time across multiple clock cycles). See
00 No operand data is displayed.
01 Capture all write data.
10 Capture all read data.
11 Capture all read and write data.
User halt enable. Selects the CPU privilege level required to execute the HALT instruction.
0 HALT is a supervisor-only instruction.
1 HALT is a supervisor/user instruction.
Branch target bytes. Defines the number of bytes of branch target address DDATA displays.
00 0 bytes
01 Lower 2 bytes of the target address
10 Lower 3 bytes of the target address
11 Entire 4-byte target address
See
Reserved, should be cleared.
Non- mode. Determines whether the core operates in pipelined or mode or not.
0 Pipelined mode
1 Nonpipelined mode. The processor effectively executes one instruction at a time with no overlap. This
Regardless of the NPL state, a triggered PC breakpoint is always reported before the triggering instruction
executes. In normal pipeline operation, the occurrence of an address and/or data breakpoint trigger is
imprecise. In non-pipeline mode, triggers are always reported before the next instruction begins execution
and trigger reporting can be considered precise.
An address or data breakpoint should always occur before the next instruction begins execution. Therefore
the occurrence of the address/data breakpoints should be guaranteed.
Ignore pending interrupts.
1
0
Single-step mode. Setting SSM puts the processor in single-step mode.
0 Normal mode.
1 Single-step mode. The processor halts after execution of each instruction. While halted, any BDM
Reserved, should be cleared.
TM = 101 or 110.
adds at least 5 cycles to the execution time of each instruction. Given an average execution latency of
1.6, throughput in non-pipeline mode would be 6.6, approximately 25% or less of pipelined performance.
command can be executed. On receipt of the
and halts again. This process continues until SSM is cleared.
Core ignores any pending interrupt requests signalled while in single-instruction-step mode.
Core services any pending interrupt requests that were signalled while in single-step mode.
Section 5.3.1, “Begin Execution of Taken Branch (PST =
MCF5272 ColdFire
Mode.”
Table 5-8. CSR Field Descriptions (continued)
®
Integrated Microprocessor User’s Manual, Rev. 3
Description
GO
command, the processor executes the next instruction
0x5).”
Table
5-2.
Section 5.6.1.1,
Debug Support
5-11