MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 366

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

UART Modules
16.3.2
UART mode registers 2 (UMR2n) control UART module configuration. UMR2n can be read or written
when the mode register pointer points to it, which occurs after any access to UMR1n. UMR2n accesses do
not update the pointer.
Table 16-3
16-6
Bits
7–6
3–0
5
4
Address
Reset
TxCTS Transmitter clear-to-send. If both TxCTS and TxRTS are enabled, TxCTS controls the operation of the
TxRTS Transmitter ready-to-send. Controls negation of RTS to automatically terminate a message transmission when
Name
Field
R/W
CM
SB
describes UMR2n fields.
UART Mode Register 2 (UMR2n)
Channel mode. Selects a channel mode.
00 Normal
01 Automatic echo
10 Local loop-back
11 Remote loop-back
the transmitter is disabled after completion of a transmission. Attempting to program a receiver and transmitter
in the same channel for RTS control is not permitted and disables RTS control for both.
0 The transmitter has no effect on RTS.
1 When the transmitter is disabled after transmission completes, setting this bit automatically clears
transmitter.
0 CTS has no effect on the transmitter.
1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a
Stop-bit length control. Selects the length of the stop bit appended to the transmitted character. Stop-bit lengths
of 9/16th to 2 bits are programmable for 6–8 bit characters. Lengths of 1 1/16th to 2 bits are programmable for
5-bit characters. In all cases, the receiver checks only for a high condition at the center of the first stop-bit
position, that is, one bit time after the last data bit or after the parity bit, if parity is enabled. If an external 1x
clock is used for the transmitter, clearing bit 3 selects one stop bit and setting bit 3 selects 2 stop bits for
transmission.
UOP[RTS] one bit time after any characters in the channel transmitter shift and holding registers are
completely sent, including the programmed number of stop bits.
character. If CTS is asserted, the character is sent; if it is negated, the channel TxD remains in the high state
and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect
its transmission.
7
0000
0001
0010
0011
SB
CM
MBAR + 0x100, 0x140. After UMR1n is read or written, the pointer points to UMR2n.
MCF5272 ColdFire
5 Bits
1.063
1.125
1.188
1.250
6
Figure 16-3. UART Mode Register 2 (UMR2n)
6–8 Bits
0.563
0.625
0.688
0.750
Table 16-3. UMR2n Field Descriptions
TxRTS
®
5
Integrated Microprocessor User’s Manual, Rev. 3
0100
0101
0110
0111
SB
TxCTS
Section 16.5.3, “Looping
5 Bits
1.313
1.375
1.438
1.500
4
0000_0000
Description
R/W
6–8 Bits
0.813
0.875
0.938
1.000
3
1000
1001
1010
1011
SB
Modes,” describes individual modes.
5–8 Bits
1.563
1.625
1.688
1.750
SB
Freescale Semiconductor
1100
1101
1110
1111
SB
5–8 Bits
1.813
1.875
1.938
2.000
0