MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 36

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Table
Number
19-9
Bus Width Selection19-38
19-10
Mode Selection19-38
20-1
20-2
Address Decoding Priority20-4
20-3
20-4
for 16-Bit Data Bus—SRAM Cycles20-6
20-5
for 16-Bit Data Bus—SDRAM Cycles20-6
20-6
20-7
21-1
21-2
23-1
23-2
23-3
23-4
23-5
23-6
23-7
23-8
23-9
23-10
23-11
23-12
23-13
23-14
23-15
23-16
23-17
23-18
23-19
23-20
23-21
23-22
23-23
23-24
23-25
A-1
A-2
A-3
xxxvi
MCF5272 CS0 Memory
MCF5272 High Impedance
Chip Select Memory
Byte Strobe Operation for 32-Bit Data Bus ........................................................................... 20-6
Data Bus Requirement for Read/Write Cycles...................................................................... 20-7
External Bus Interface Codes for CSBRs ............................................................................. 20-8
JTAG Signals ........................................................................................................................ 21-2
Instructions............................................................................................................................ 21-7
Maximum Supply, Input Voltage and Storage Temperature ................................................. 23-1
Operating Temperature......................................................................................................... 23-2
Thermal Resistance .............................................................................................................. 23-2
I/O Driver Capability .............................................................................................................. 23-3
Clock Input and Output Timing Specifications ...................................................................... 23-5
Processor Bus Input Timing Specifications........................................................................... 23-6
Processor Bus Output Timing Specifications ........................................................................ 23-8
Debug AC Timing Specification .......................................................................................... 23-13
SDRAM Interface Timing Specifications ............................................................................. 23-14
MII Receive Signal Timing .................................................................................................. 23-17
MII Transmit Signal Timing ................................................................................................. 23-18
MII Async Inputs Signal Timing........................................................................................... 23-19
MII Serial Management Channel Timing............................................................................. 23-20
Timer Module AC Timing Specifications ............................................................................. 23-21
UART Modules AC Timing Specifications........................................................................... 23-22
IDL Master Mode Timing, PLIC Ports 1, 2, and 3 ............................................................... 23-23
IDL Slave Mode Timing, PLIC Ports 0–3 ............................................................................ 23-24
GCI Slave Mode Timing, PLIC Ports 0–3............................................................................ 23-25
GCI Master Mode Timing, PLIC PORTs 1, 2, 3 .................................................................. 23-26
General-Purpose I/O Port AC Timing Specifications .......................................................... 23-28
USB Interface AC Timing Specifications............................................................................. 23-29
IEEE 1149.1 (JTAG) AC Timing Specifications .................................................................. 23-30
QSPI Modules AC Timing Specifications ............................................................................ 23-31
PWM Modules AC Timing Specifications............................................................................ 23-32
On-Chip Module Base Address Offsets from MBAR...............................................................A-1
CPU Space Registers Memory Map .......................................................................................A-2
On-Chip Peripherals and Configuration Registers Memory Map ............................................A-2
ColdFire Bus Signal Summary ............................................................................................. 20-1
Byte Strobe Operation
Byte Strobe Operation
DC Electrical Specifications ................................................................................................. 23-3
MCF5272 ColdFire
List of Tables (Continued)
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Integrated Microprocessor User’s Manual, Rev. 3
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Freescale Semiconductor
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