MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 301

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16.4.1
SARn, shown in
Freescale Semiconductor
1
Channel
The DMA module originally supported a left-justified 16-bit byte count register (BCR). This function was later
reimplemented as a right-justified 24-bit BCR. The operation of the DMA and the interpretation of the BCR is controlled
by the MPARK[BCR24BIT]. See
DMA
0
1
2
3
Source Address Registers (SAR0–SAR3)
IPSBAR
0x1CC
0x1CC
Offset
0x10C
0x10C
0x14C
0x14C
0x18C
0x18C
0x1C0
0x1C4
0x1C8
0x1D0
0x100
0x104
0x108
0x110
0x140
0x144
0x148
0x150
0x180
0x184
0x188
0x190
Figure
Table 16-2. Memory Map for DMA Controller Module Registers
DMA status register 0
DMA status register 1
DMA status register 2
DMA status register 3
(DSR0) [p. 16-10]
(DSR1) [p. 16-10]
(DSR2) [p. 16-10]
(DSR3) [p. 16-10]
16-4, contains the address from which the DMA controller requests data.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Byte count register 0 (BCR24BIT = 0)
Byte count register 1 (BCR24BIT = 0)
Byte count register 2 (BCR24BIT = 0)
Byte count register 3 (BCR24BIT = 0)
Reserved
Reserved
Reserved
Reserved
[31:24]
Section 8.5.3, “Bus Master Park Register
Destination address register 0 (DAR0) [p. 16-6]
Destination address register 1 (DAR1) [p. 16-6]
Destination address register 2 (DAR2) [p. 16-6]
Destination address register 3 (DAR3) [p. 16-6]
Source address register 0 (SAR0) [p. 16-5]
Source address register 1 (SAR1) [p. 16-5]
Source address register 2 (SAR2) [p. 16-5]
Source address register 3 (SAR3) [p. 16-5]
DMA control register 0 (DCR0) [p. 16-7]
DMA control register 1 (DCR1) [p. 16-7]
DMA control register 2 (DCR2) [p. 16-7]
DMA control register 3 (DCR3) [p. 16-7]
Byte count register 0 (BCR24BIT = 1)
Byte count register 2 (BCR24BIT = 1)
[23:16]
Byte count register 1 (BCR24BIT = 1)
Byte count register 3 (BCR24BIT = 1)
1
1
1
1
(MPARK)" for more details.
Reserved
Reserved
Reserved
Reserved
[15:8]
Reserved
Reserved
Reserved
Reserved
1
1
1
1
(BCR3) [p. 16-7]
(BCR0) [p. 16-7]
(BCR1) [p. 16-7]
(BCR2) [p. 16-7]
DMA Controller Module
[7:0]
16-5