MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 606

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Queued Analog-to-Digital Converter (QADC)
28.10 Interrupts
The four interrupt lines are outputs of the module and have no priority or arbitration within the module.
28.10.1 Interrupt Operation
QADC inputs can be monitored by polling or by using interrupts. When interrupts are not needed, the
completion flag and the pause flag for each queue can be monitored in the status register (QASR0). In other
words, flag bits can be polled to determine when new results are available.
Table 28-26
activity.
If interrupts are enabled for an event, the QADC requests interrupt service when the event occurs. Using
interrupts does not require continuously polling the status flags to see if an event has taken place; however,
status flags must be cleared after an interrupt is serviced, in order to remove the interrupt request
In both polled and interrupt-driven operating modes, status flags must be re-enabled after an event occurs.
Flags are re-enabled by clearing the appropriate QASR0 bits in a particular sequence. QASR0 must first
be read, then 0s must be written to the flags that are to be cleared. If a new event occurs between the time
that the register is read and the time that it is written, the associated flag is not cleared.
28.10.2 Interrupt Sources
The QADC includes four sources of interrupt requests, each of which is separately enabled. Each time the
result is written for the last conversion command word (CCW) in a queue, the completion flag for the
corresponding queue is set, and when enabled, an interrupt is requested. In the same way, each time the
28-68
shows the status flag and interrupt enable bits which correspond to queue 1 and queue 2
Queue 1
Queue 2
Leakage below 200 nA is obtainable only within a limited temperature
range.
Queue
Source Impedance
100 kΩ
10 kΩ
1 kΩ
Result written for last CCW in queue 1
Result written for a CCW with pause bit set in queue 1
Result written for last CCW in queue 2
Result written for a CCW with pause bit set in queue 2
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 28-26. QADC Status Flags and Interrupt Sources
Table 28-25. Error Resulting from Input Leakage (I
0.2 counts
Queue Activity
2 counts
100 nA
—
CAUTION
Leakage Value (10-Bit Conversions)
0.4 counts
200 nA
4 count
—
0.1 counts
10 counts
1 counts
500 nA
Status
Flag
CF1
CF2
PF1
PF2
Off
)
0.2 counts
20 counts
Enable Bit
1000 nA
2 counts
Interrupt
CIE1
PIE1
CIE2
PIE2
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