LAN7500-ABZJ

Manufacturer Part NumberLAN7500-ABZJ
DescriptionIC USB-10/100/1K ETH CTRL 56QFN
ManufacturerSMSC
LAN7500-ABZJ datasheets
 


Specifications of LAN7500-ABZJ

Mfg Application NotesLAN7500 SchematicDesign ResourcesLAN7500 BOM
Controller TypeEthernet Controller, USB 2.0 to 10/100/1KInterfaceUSB/Serial
Voltage - Supply1.2V, 2.5V, 3.3VOperating Temperature0°C ~ 70°C
Mounting TypeSurface MountPackage / Case56-VFQFN Exposed Pad
Lead Free Status / RoHS StatusLead free / RoHS CompliantCurrent - Supply-
Other names638-1108  
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Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller
Datasheet
7.5.3
Power-On Reset Timing
Figure 7.3
illustrates the nRESET timing requirements in relation to power-on. A hardware reset
(nRESET assertion) is required following power-on. For proper operation, nRESET must be asserted
for no less than t
. The nRESET pin can be asserted at any time, but must not be deasserted before
rstia
t
after all external power supplies have reached operational levels.
purstd
All External
V
opp
Power Supplies
nRESET
Table 7.16 nRESET Power-On Timing Values
SYMBOL
t
External power supplies at operational level to nRESET
purstd
deassertion
t
External power supplies at at operational level to
purstv
nRESET valid
t
nRESET input assertion time
rstia
Note: nRESET deassertion must be monotonic.
SMSC LAN7500/LAN7500i
t
purstd
t
t
purstv
rstia
Figure 7.3 nRESET Power-On Timing
DESCRIPTION
49
DATASHEET
MIN
TYP
MAX
UNITS
25
mS
0
nS
μS
100
Revision 1.0 (11-01-10)