LAN7500-ABZJ

Manufacturer Part NumberLAN7500-ABZJ
DescriptionIC USB-10/100/1K ETH CTRL 56QFN
ManufacturerSMSC
LAN7500-ABZJ datasheets
 


Specifications of LAN7500-ABZJ

Mfg Application NotesLAN7500 SchematicDesign ResourcesLAN7500 BOM
Controller TypeEthernet Controller, USB 2.0 to 10/100/1KInterfaceUSB/Serial
Voltage - Supply1.2V, 2.5V, 3.3VOperating Temperature0°C ~ 70°C
Mounting TypeSurface MountPackage / Case56-VFQFN Exposed Pad
Lead Free Status / RoHS StatusLead free / RoHS CompliantCurrent - Supply-
Other names638-1108  
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1.1.2
USB
The USB portion of the LAN7500/LAN7500i integrates a Hi-Speed USB 2.0 device controller and USB
PHY.
The USB device controller contains a USB low-level protocol interpreter which implements the USB
bus protocol, packet generation/extraction, PID/Device ID parsing, and CRC coding/decoding, with
autonomous error handling. The USB device controller is capable of operating in USB 2.0 Hi-Speed
and Full-Speed compliant modes and contains autonomous protocol handling functions such as
handling of suspend/resume/reset conditions, remote wakeup, and stall condition clearing on Setup
packets. The USB device controller also autonomously handles error conditions such as retry for CRC
and data toggle errors, and generates NYET, STALL, ACK and NACK handshake responses,
depending on the endpoint buffer status.
The LAN7500/LAN7500i implements four USB endpoints: Control, Interrupt, Bulk-in, and Bulk-out. The
Bulk-in and Bulk-out Endpoints allow for Ethernet reception and transmission respectively.
Implementation of vendor-specific commands allows for efficient statistics gathering and access to the
device’s system control and status registers.
1.1.3
FIFO Controller
The FIFO controller uses two internal SRAMs to buffer RX and TX traffic. Bulk-Out packets from the
USB controller are directly stored into the TX buffer. The FIFO Controller is responsible for extracting
Ethernet frames from the USB packet data and passing the frames to the MAC. Received Ethernet
Frames are filtered by the Receive Filtering Engine and frames meeting the filtering constraints are
stored into the RX buffer and become the basis for bulk-in packets.
1.1.4
Ethernet
The LAN7500/LAN7500i integrates an IEEE 802.3/802.3u/802.3ab compliant PHY for twisted pair
Ethernet applications and a 10/100/1000 Ethernet Media Access Controller (MAC).
The PHY can be configured for 1000 Mbps (1000BASE-T), 100 Mbps (100BASE-TX) or 10 Mbps
(10BASE-T) operation in Full-Duplex mode. It can be configured for 100 Mbps or 10 Mbps operation
in Half Duplex mode. The PHY block includes auto-negotiation, auto-polarity correction, and Auto-
MDIX. Minimal external components are required for the utilization of the Integrated PHY.
The Ethernet MAC/PHY supports numerous power management wakeup features, including “Magic
Packet”, “Wake on LAN”, and “Link Status Change”. Microsoft NDIS 6.2 and Windows 7 compliant ARP
and NS offload support is also provided.The device will respond to an NS or ARP request by
generating and transmitting a response. When received in a SUSPEND state, an NS or ARP request
will not result in the generation of a wake event. Additionally, five status LEDs are supported.
1.1.5
Frame Filtering
The LAN7500/LAN7500i Receive Filtering Engine performs frame filtering. It supports 33 perfect
address filters. These can be used to filter either the Ethernet source address or destination address.
Additional address filtering is available via a 512-bit hash filter. The hash filter can perform unicast or
multicast filtering.
VLAN tagged frames can be filtered via the VLAN ID. A 4096-bit table exists to support all possible
VLAN IDs. The VLAN type can be programmed. Double tagging is supported.
Revision 1.0 (11-01-10)
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller
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DATASHEET
Datasheet
SMSC LAN7500/LAN7500i