LFE2-12E-5TN144C Lattice, LFE2-12E-5TN144C Datasheet - Page 100

• Manufacturer Part Number: LFE2-12E-5TN144C
• Description: FPGA - Field Programmable Gate Array 12K LUTs 93 I/O DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFE2-12E-5TN144C

• Number Of Macrocells: 12000
• Number Of Programmable I/os: 93
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 3-15. sysCONFIG Parallel Port Write Cycle
Figure 3-16. sysCONFIG Slave Serial Port Timing
Figure 3-17. Power-On-Reset (POR) Timing
CCLK (input)
WRITEN
1. In Master Parallel Mode the FPGA provides CCLK. In Slave Parallel Mode the external device provides CCLK.
V
1. Time taken from V
2. Device is in a Master Mode.
3. The CFG pins are normally static (hard wired).
CCLK
CS1N
BUSY
D[0:7]
CC
CSN
DOUT
/V
CFG[2:0]
DIN
CCAUX
DONE
CCLK
INITN
1
1
2
3
CC
or V
t
SUCBDI
CCAUX
, whichever is the last to reach its V
t
t
SUWD
SUCS
Byte 0
t
SUSCDI
t
ICFG
t
SUCFG
t
BSCL
3-48
Byte 1
t
SSCL
t
HCBDI
t
VMC
Valid
Byte 2
MIN
t
DCB
DC and Switching Characteristics
.
LatticeECP2/M Family Data Sheet
t
t
HCFG
BSCYC
t
t
BSCH
CODO
t
SSCH
Byte n
t
HSCDI
t
HCS
t
HWD