LFE2-12E-5TN144C Lattice, LFE2-12E-5TN144C Datasheet - Page 389

• Manufacturer Part Number: LFE2-12E-5TN144C
• Description: FPGA - Field Programmable Gate Array 12K LUTs 93 I/O DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFE2-12E-5TN144C

• Number Of Macrocells: 12000
• Number Of Programmable I/os: 93
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
November 2009
March 2010
April 2011
July 2010
(cont.)
Date
Version
(cont.)
03.5
03.6
03.7
03.8
Ordering Information
Pinout Information
Pinout Information
Pinout Information
Pinout Information
DC and Switching
DC and Switching
Characteristics
Characteristics
Architecture
All Sections
Section
(cont.)
LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70
and LFE2M100 table - corrected values for LFE2M50, 672
fpBGA in Available DDR-Interfaces per I/O Bank.
Minor corrections in LFE2M20E/SE and LFE2M35E/SE Logic
Signal Connections: 484 fpBGA table.
Minor corrections in LFE2M50E/SE and LFE2M70E/SE Logic
Signal Connections: 900 fpBGA table.
Minor corrections in LFE2M100E/SE Logic Signal Connections:
900 fpBGA table.
Updated LFE2-6E/SE and LFE2-12E/SE Logical Signal Connec-
tions (changed D1/SPIDS to D1).
Updated LatticeECP2M Part Number Description diagram.
Footnote for SED operating frequency added to the sysCONFIG
Port Timing Specifications table.
Changed Dual Function pin E7 to be D7/SPDI0 in Logic Signal
Connections tables. Changed footnote (***) in Logic Signal Con-
nections table.
Updated the Typical sysIO Behavior During Power-up text sec-
tion.
Added reference to powerup information.
Corrected reference to footnote for pins 131 and 132 for the
LFE-20E/SE, 208 PQFP.
Referenced footnote (***) for all D7/SPID0.
Changed D7*** to D7/SPID0.
Corrected *** footnote.
Included references to Lattice Diamond design software wher-
ever ispLEVER and ispLeverCORE is specified.
DC Electrical Characteristics table:
- Added footnote 3 to I
- Added footnote 2 to I
- Updated C1 and C2 typ. and max. data.
DLL Timing table – Removed line for t
LatticeECP2/M sysCONFIG Port Timing Specifications table –
added footnote to t
Figure 3-18 – Corrected label to be PRGM (not PRGMRJ).
LFE2-12E/SE and LFE-20/SE Logical Signal Connections for
208 PQFP – Corrected Dual Function information for pins 112,
114, 117, 119.
7-4
DINIT
LatticeECP2/M Family Data Sheet
IH
IL
.
Change Summary
, I
IH
R
and t
Revision History
F
.