LFE2-12E-5TN144C Lattice, LFE2-12E-5TN144C Datasheet - Page 308

• Manufacturer Part Number: LFE2-12E-5TN144C
• Description: FPGA - Field Programmable Gate Array 12K LUTs 93 I/O DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFE2-12E-5TN144C

• Number Of Macrocells: 12000
• Number Of Programmable I/os: 93
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA
Lattice Semiconductor
Number
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
*** These sysCONFIG pins are dedicated I/O pins for configuration. The outpus are actively driven during normal device operation.
****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.
Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one con-
nection with a package ball or pin.
Ball
V18
Function
Ball/Pad
VCCPLL
LFE2M50E/SE
Bank
-
Dual Function
Differential
4-205
Function
Ball/Pad
VCCPLL
LatticeECP2/M Family Data Sheet
Bank
-
LFE2M70E/SE
Dual Function
Pinout Information
Differential