LFE2-12E-5TN144C Lattice, LFE2-12E-5TN144C Datasheet - Page 67

• Manufacturer Part Number: LFE2-12E-5TN144C
• Description: FPGA - Field Programmable Gate Array 12K LUTs 93 I/O DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFE2-12E-5TN144C

• Number Of Macrocells: 12000
• Number Of Programmable I/os: 93
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
RSDS
The LatticeECP2/M devices support differential RSDS standard. This standard is emulated using complementary
LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup-
ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS
standard implementation. Resistor values in Figure 3-4 are industry standard values for 1% resistors.
Figure 3-4. RSDS (Reduced Swing Differential Signaling)
Table 3-5. RSDS DC Conditions
8mA
8mA
V CCIO = 2.5V
V CCIO = 2.5V
V
Z
R
R
R
V
V
V
V
Z
I
1. For input buffer, see LVDS table.
Parameter
DC
OUT
BACK
CCIO
OH
OL
OD
CM
S
P
T
On-chip
(+/-5%)
(+/-5%)
Output Driver Supply (+/-5%)
Driver Impedance
Driver Series Resistor (+/-1%)
Driver Parallel Resistor (+/-1%)
Receiver Termination (+/-1%)
Output High Voltage
Output Low Voltage
Output Differential Voltage
Output Common Mode Voltage
Back Impedance
DC Output Current
1
Over Recommended Operating Conditions
R
R
S
S
Off-chip
= 294 ohms
= 294 ohms
(+/-1%)
(+/-1%)
Description
R
P
Zo = 100 ohm differential
= 121 ohms
(+/-1%)
3-15
Transmission line,
R
T
DC and Switching Characteristics
= 100 ohms
LatticeECP2/M Family Data Sheet
(+/-1%)
Typical
101.5
2.50
1.35
1.15
0.20
1.25
3.66
294
121
100
20
Off-chip
Units
mA
V




V
V
V
V

On-chip
+
-