JS28F128P30BF75A NUMONYX, JS28F128P30BF75A Datasheet - Page 44

• Manufacturer Part Number: JS28F128P30BF75A
• Description: IC FLASH 128MBIT 65NM 56TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of JS28F128P30BF75A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (8Mx16)
• Speed: 75ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-TFSOP (0.551", 14.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 14: Example Latency Count Setting using Code 3
11.2.3
11.2.3.1
Table 21: WAIT Functionality Table (Sheet 1 of 2)
Datasheet
44
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’
CE# =’0’, OE# = ‘0’
Synchronous Array Reads
Synchronous Non-Array Reads
A[MAX:0]
D[15:0]
ADV#
CLK
CE#
WAIT Polarity
The WAIT Polarity bit (WP), RCR[10] determines the asserted level (V
WAIT. When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is
asserted low. WAIT changes state on valid clock edges during active bus cycles (CE#
asserted, OE# asserted, RST# deasserted).
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-array read mode, such as read
status, read ID, or read CFI. The WAIT signal is also “deasserted” when data is valid on
the bus.
WAIT behavior during synchronous non-array reads at the end of word line works
correctly only on the first data access.
When the device is operating in asynchronous page mode, asynchronous single word
read mode, and all write operations, WAIT is set to a deasserted state as determined
by RCR[10]. See
page
60, and
Condition
Figure 23, “Asynchronous Page-Mode Read Timing” on page
Figure 22, “Asynchronous Single-Word Read (ADV# Latch)” on
0
Code 3
1
High-Z
R103
Address
High-Z
Active
Active
Active
2
WAIT
3
t
Data
Data
4
OH
or V
61.
OL
August 2008
306666-12
) of
Notes
1
1
1
1
P30