S25FL128P0XNFI001 Spansion Inc., S25FL128P0XNFI001 Datasheet - Page 14

no-image

S25FL128P0XNFI001

Manufacturer Part Number
S25FL128P0XNFI001
Description
IC, FLASH, 128MBIT, 104MHZ, WSON-8
Manufacturer
Spansion Inc.
Datasheet

Specifications of S25FL128P0XNFI001

Memory Type
Flash
Memory Size
128Mbit
Ic Interface Type
Serial, SPI
Clock Frequency
104MHz
Supply Voltage Range
2.7 To 3.6 V
Memory Case Style
WSON
No. Of Pins
8
Cell Type
NOR
Density
128Mb
Access Time (max)
20ns
Interface Type
Parallel/Serial-SPI
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
WSON
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Async/Sync
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
1b
Number Of Words
128M
Supply Current
22mA
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S25FL128P0XNFI001
Manufacturer:
SPANSION
Quantity:
300
Part Number:
S25FL128P0XNFI001
Manufacturer:
VISION
Quantity:
2 300
7.7
8. Sector Address Table
14
Hold Mode (HOLD#)
The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write
Status Register, program or erase operation that is currently in progress.
The Hold mode starts on the falling edge of HOLD# if SCK is also low (see
use). If the falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling
edge of SCK (non-standard use).
The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge
of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-
standard use) See
The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the
Hold mode.
CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains
unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the
device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high,
followed by driving CS# low.
Table 8.1
program data before the data is programmed into the memory array. Each page or byte can be individually
programmed (bits are changed from 1 to 0). The data is erased (bits are changed from 0 to 1) on a sector- or
device-wide basis using the SE or BE commands.
sector. The complete set of sectors comprises the memory array of the Flash device.
HOLD#
64 (256 KB sector)
256 (64 KB sector)
Each Device has
SCK
16,777,216
shows the size of the memory array, sectors, and pages. The device uses pages to cache the
65,536
Figure
7.1.
262144 (256 KB sector)
Table 8.1 S25FL128P Device Organization
65536 (64 KB sector)
1024 (256 KB sector)
256 (64 KB sector)
Each Sector has
(standard use)
Condition
Figure 7.1 Hold Mode Operation
Hold
S25FL128P
D a t a
Table 8.2
S h e e t
shows the starting and ending address for each
Each Page has
(non-standard use)
256
Condition
S25FL128P_00_08 September 8, 2009
Hold
Figure 7.1 on page
bytes
pages
sectors
14, standard

Related parts for S25FL128P0XNFI001