S25FL128P0XNFI001 Spansion Inc., S25FL128P0XNFI001 Datasheet - Page 26

• Manufacturer Part Number: S25FL128P0XNFI001
• Description: IC, FLASH, 128MBIT, 104MHZ, WSON-8
• Manufacturer: Spansion Inc.

Specifications of S25FL128P0XNFI001

• Memory Type: Flash
• Memory Size: 128Mbit
• Ic Interface Type: Serial, SPI
• Clock Frequency: 104MHz
• Supply Voltage Range: 2.7 To 3.6 V
• Memory Case Style: WSON
• No. Of Pins: 8
• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 20ns
• Interface Type: Parallel/Serial-SPI
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: WSON
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 1b
• Number Of Words: 128M
• Supply Current: 22mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.6
11.7
26
11.7.1
Write Disable (WRDI: 04h)
Read Status Register (RDSR: 05h)
Serial Mode
The Write Disable (WRDI) command (see
disables the device from accepting a Write Status Register, program, or erase command. The host system
must first drive CS# low, write the WRDI command, and then drive CS# high.
Any of following conditions resets the WEL bit:
The Read Status Register (RDSR) command outputs the state of the Status Register bits.
the status register bits and their functions.
The RDSR command may be written at any time, even while a program, erase, or Write Status Register
operation is in progress. The host system should check the Write In Progress (WIP) bit before sending a new
command to the device if an operation is already in progress.
sequence, which also shows that it is possible to read the Status Register continuously until CS# is driven
high.
Power-up
Write Disable (WRDI) command completion
Write Status Register (WRSR) command completion
Page Program (PP) command completion
Sector Erase (SE) command completion
Bulk Erase (BE) command completion
Bit
7
6
5
4
3
2
1
0
Status Register Bit
Don’t Care
SRWD
WEL
BP2
BP1
BP0
WIP
0
Table 11.3 S25FL128P Status Register (Uniform 256 KB sector)
Figure 11.9 Write Disable (WRDI) Command Sequence
SO/PO[7-0]
Status Register Write
Write Enable Latch
Write in Progress
SCK
CS#
Block Protect
Bit Function
SI
Disable
—
—
S25FL128P
Mode 3
Mode 0
Hi-Z
Figure
D a t a
11.9) resets the Write Enable Latch (WEL) bit to a 0, which
0 1 2 3 4 5 6 7
1 = Protects when WP#/ACC is low
0 = No protection, even when WP#/ACC is low
—
Not used
000–111 = Protects upper half of address range in 7 sizes.
1 = Device accepts Write Status Register, program, or erase commands
0 = Ignores Write Status Register, program, or erase commands
1 = Device Busy. A Write Status Register, program, or erase operation is
in progress
0 = Ready. Device is in standby mode and can accept commands.
S h e e t
Command
Figure 11.10
S25FL128P_00_08 September 8, 2009
shows the RDSR command
Description
Table 11.3
shows