S25FL128P0XNFI001 Spansion Inc., S25FL128P0XNFI001 Datasheet - Page 19

• Manufacturer Part Number: S25FL128P0XNFI001
• Description: IC, FLASH, 128MBIT, 104MHZ, WSON-8
• Manufacturer: Spansion Inc.

Specifications of S25FL128P0XNFI001

• Memory Type: Flash
• Memory Size: 128Mbit
• Ic Interface Type: Serial, SPI
• Clock Frequency: 104MHz
• Supply Voltage Range: 2.7 To 3.6 V
• Memory Case Style: WSON
• No. Of Pins: 8
• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 20ns
• Interface Type: Parallel/Serial-SPI
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: WSON
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 1b
• Number Of Words: 128M
• Supply Current: 22mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11. Command Definitions
11.1
September 8, 2009 S25FL128P_00_08
11.1.1
Read Data Bytes (READ: 03h)
Serial Mode
The host system must shift all commands, addresses, and data in and out of the device, beginning with the
most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte
command on SI (all commands are one byte long), most significant bit first. Each successive bit is latched on
the rising edge of SCK.
Every command sequence begins with a one-byte command code. The command may be followed by
address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the
command sequence has been written.
The Read Data Bytes (READ), Read Status Register (RDSR), Read Data Bytes at Higher Speed
(FAST_READ) and Read Identification (RDID) command sequences are followed by a data output sequence
on SO. CS# can be driven high after any bit of the sequence is output to terminate the operation.
The Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable
(WREN), or Write Disable (WRDI) commands require that CS# be driven high at a byte boundary, otherwise
the command is not executed. Since a byte is composed of eight bits, CS# must therefore be driven high
when the number of clock pulses after CS# is driven low is an exact multiple of eight.
The device ignores any attempt to access the memory array during a Write Status Register, program, or
erase operation, and continues the operation uninterrupted.
The Read Data Bytes (READ-Serial Mode) command reads data from the memory array at the frequency
(f
device by driving CS# low. The READ command is then written to SI, followed by a 3-byte address (A23-A0).
Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on
SO at a frequency f
Figure 11.1
location. The device automatically increments to the next higher address after each byte of data is output.
The entire memory array can therefore be read with a single READ command. When the highest address is
reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely.
The READ command is terminated by driving CS# high at any time during data output. The device rejects any
READ command issued while it is executing a program, erase, or Write Status Register operation, and
continues the operation uninterrupted.
SCK
CS#
SCK
SI
SO
) presented at the SCK input, with a maximum speed of 40 MHz. The host system must first select the
Mode 3
Mode 0
Hi-Z
and
Table 11.6
0
SCK
1
, on the falling edge of SCK.
Command
Table 11.6 on page 38
Figure 11.1 Read Data Bytes (READ) Command Sequence
2
D a t a
3
detail the READ command sequence. The first byte specified can be at any
4
5
S h e e t
6
S25FL128P
7
MSB
23 22 21
8
9
lists the complete set of commands.
24-Bit Address
10
3 2 1 0
28
29
30
31 32 33 34 35 36 37 38 39
MSB
7 6 5
Data Out 1
4
3 2 1 0 7
Data Out 2
19