P89LPC912FDH NXP Semiconductors, P89LPC912FDH Datasheet
P89LPC912FDH
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P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core flash with 128-byte RAM Rev. 05 — 28 September 2007 1. General description The P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin packages, based on a high performance processor architecture ...
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... NXP Semiconductors I Serial flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. I Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from eight values. I Low voltage reset (brownout detect) allows a graceful system shutdown when power fails. May optionally be confi ...
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... Name P89LPC912FDH TSSOP14 P89LPC912HDH P89LPC913FDH P89LPC914FDH 4.1 Ordering options Table 3. Type number P89LPC912FDH P89LPC912HDH P89LPC913FDH P89LPC914FDH P89LPC912_913_914_5 Product data sheet 8-bit microcontrollers with two-clock 80C51 core highlights the differences between these three devices. For a complete list of Section 2 “Features” on page X2 CLKOUT ...
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... NXP Semiconductors 5. Block diagram P89LPC912 P3[1:0] P2[5:2] P1.2, P1.5 P0.2, P0[6:4] OSCILLATOR DIVIDER XTAL1 CRYSTAL OR XTAL2 RESONATOR Fig 1. P89LPC912 block diagram P89LPC912_913_914_5 Product data sheet 8-bit microcontrollers with two-clock 80C51 core HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU 1 kB CODE FLASH internal bus ...
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... NXP Semiconductors P89LPC913 P3[1:0] P2.2, P2.3, P2.5 P1.0, P1.1, P1.5 P0.2, P0[6:4] OSCILLATOR DIVIDER XTAL1 CRYSTAL OR XTAL2 RESONATOR Fig 2. P89LPC913 block diagram P89LPC912_913_914_5 Product data sheet 8-bit microcontrollers with two-clock 80C51 core HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU 1kB CODE FLASH ...
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... NXP Semiconductors P89LPC914 1 kB CODE FLASH 128 BYTE DATA RAM P2[5:2] CONFIGURABLE I/O P1.5, P1[2:0] CONFIGURABLE I/O P0.2, P0[6:4] CONFIGURABLE I/O KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE OSCILLATOR DIVIDER OSCILLATOR Fig 3. P89LPC914 block diagram P89LPC912_913_914_5 Product data sheet 8-bit microcontrollers with two-clock 80C51 core ...
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... NXP Semiconductors 6. Functional diagram Fig 4. P89LPC912 functional diagram Fig 5. P89LPC913 functional diagram P89LPC912_913_914_5 Product data sheet 8-bit microcontrollers with two-clock 80C51 core KBI2 CIN2A KBI4 CIN1A PORT 0 KBI5 CMPREF KBI6 CMP1 CLKOUT XTAL2 PORT 3 XTAL1 KBI2 CIN2A KBI4 CIN1A PORT 0 KBI5 ...
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... NXP Semiconductors Fig 6. P89LPC914 functional diagram P89LPC912_913_914_5 Product data sheet 8-bit microcontrollers with two-clock 80C51 core KBI2 CIN2A KBI4 CIN1A PORT 0 KBI5 CMPREF KBI6 CMP1 Rev. 05 — 28 September 2007 P89LPC912/913/914 TXD RXD T0 PORT 1 RST P89LPC914 MOSI MISO PORT 2 SS SPICLK 002aaa477 © ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 7. P89LPC912 TSSOP14 pin configuration Fig 8. P89LPC913 TSSOP14 pin configuration Fig 9. P89LPC914 TSSOP14 pin configuration P89LPC912_913_914_5 Product data sheet P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core P2.2/MOSI 1 2 P2.5/SPICLK P1.5/RST 3 P89LPC912 P0.6/CMP1/KBI6 P1 ...
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... NXP Semiconductors 7.2 Pin description Table 4. P89LPC912 pin description Symbol Pin Type P0.2, P0.4 to I/O P0.6 P0.2/CIN2A/ 13 I/O KBI2 I I P0.4/CIN1A/ 12 I/O KBI4 I I P0.5/CMPREF/ 11 I/O KBI5 I I P0.6/CMP1/ 5 I/O KBI6 O I P1.2, P1.5 I/O (P1.2); I (P1.5) P1.2/T0 6 I/O I/O P1.5/RST ...
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... NXP Semiconductors Table 4. P89LPC912 pin description Symbol Pin Type P2.2 to P2.5 I/O P2.2/MOSI 1 I/O I/O P2.3/MISO 14 I/O I/O P2.4/SS 9 I/O I P2.5/SPICLK 2 I/O I/O P3.0 to P3.1 I/O P3.0/XTAL2/ 8 I/O CLKOUT O O P3.1/XTAL1 7 I P89LPC912_913_914_5 Product data sheet 8-bit microcontrollers with two-clock 80C51 core … ...
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... NXP Semiconductors Table 5. P89LPC913 pin description Symbol Pin Type P0.2, I/O P0.4 to P0.6 P0.2/CIN2A/ 13 I/O KBI2 I I P0.4/CIN1A/ 12 I/O KBI4 I I P0.5/CMPREF/ 11 I/O KBI5 I I P0.6/CMP1/ 5 I/O KBI6 O I P1.0, P1.1, I/O P1.5 (P1.0, P1.1); I (P1.5) P1.0/TXD 9 I/O O P1.1/RXD 6 I/O I P1.5/RST ...
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... NXP Semiconductors Table 5. P89LPC913 pin description Symbol Pin Type P2.2, P2.3, I/O P2.5 P2.2/MOSI 1 I/O I/O P2.3/MISO 14 I/O I/O P2.5/SPICLK 2 I/O I/O P3.0 to P3.1 I/O P3.0/XTAL2/ 8 I/O CLKOUT O O P3.1/XTAL1 7 I P89LPC912_913_914_5 Product data sheet 8-bit microcontrollers with two-clock 80C51 core … ...
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... NXP Semiconductors Table 6. P89LPC914 pin description Symbol Pin Type P0.2, I/O P0.4 to P0.6 P0.2/CIN2A/ 13 I/O KBI2 I I P0.4/CIN1A/ 12 I/O KBI4 I I P0.5/CMPREF 11 I/O / KBI5 I I P0.6/CMP1/ 5 I/O KBI6 O I P1.0 to P1.2, I/O P1.5 (P1.0 to P1.2); I (P1.5) P1.0/TXD 9 I/O O P1.1/RXD 6 I/O I P1.2/T0 ...
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... NXP Semiconductors Table 6. P89LPC914 pin description Symbol Pin Type P2.2 to P2.5 I/O P2.2/MOSI 1 I/O I/O P2.3/MISO 14 I/O I/O P2.4/SS 8 I/O I P2.5/SPICLK 2 I/O I P89LPC912_913_914_5 Product data sheet 8-bit microcontrollers with two-clock 80C51 core …continued Description Port 2: Port 4-bit I/O port with a user-configurable output type. During reset Port 2 latches are confi ...
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... NXP Semiconductors 8. Functional description Remark: Please refer to the P89LPC912/913/914 User manual for a more detailed functional description. 8.1 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs. ...
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Table 7. P89LPC912 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H AUXR1 Auxiliary function register A2H Bit address B* B register F0H CMP1 Comparator 1 control register ACH CMP2 ...
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Table 7. P89LPC912 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. KBCON Keypad control register 94H KBMASK Keypad interrupt mask 86H register KBPATN Keypad pattern register 93H Bit address P0* Port 0 80H Bit ...
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Table 7. P89LPC912 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. RTCL Real-time clock register low D3H SP Stack pointer 81H SPCTL SPI control register E2H SPSTAT SPI status register E1H SPDAT SPI data ...
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Table 8. P89LPC913 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H AUXR1 Auxiliary function register A2H Bit address B* B register F0H [2] BRGR0 Baud rate generator rate low ...
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Table 8. P89LPC913 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address IP1* Interrupt priority 1 F8H IP1H Interrupt priority 1 high F7H KBCON Keypad control register 94H KBMASK Keypad interrupt mask 86H ...
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Table 8. P89LPC913 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address PSW* Program status word D0H PT0AD Port 0 digital input disable F6H RSTSRC Reset source register DFH RTCCON Real-time clock control ...
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Table 8. P89LPC913 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. WDL Watchdog load C1H WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H [1] All ports are in input only (high impedance) ...
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Table 9. P89LPC914 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H AUXR1 Auxiliary function register A2H Bit address B* B register F0H [2] BRGR0 Baud rate generator rate low ...
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Table 9. P89LPC914 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address IP0* Interrupt priority 0 B8H IP0H Interrupt priority 0 high B7H Bit address IP1* Interrupt priority 1 F8H IP1H Interrupt priority ...
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Table 9. P89LPC914 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address PSW* Program status word D0H PT0AD Port 0 digital input disable F6H RSTSRC Reset source register DFH RTCCON Real-time clock control ...
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Table 9. P89LPC914 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. WDL Watchdog load C1H WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H [1] All ports are in input only (high impedance) ...
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... NXP Semiconductors 8.2 Enhanced CPU The P89LPC912/913/914 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. 8.3 Clocks 8.3.1 Clock definitions The P89LPC912/913/914 device has several internal clocks as defined below: OSCCLK — ...
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... NXP Semiconductors 8.3.6 Clock output (P89LPC912, P89LPC913) The P89LPC912 supports a user selectable clock output function on the XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on X1) and if the Real-Time clock is not using the crystal oscillator as its clock source ...
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... NXP Semiconductors Fig 10. Block diagram of oscillator control (P89LPC912) XTAL1 XTAL2 Fig 11. Block diagram of oscillator control (P89LPC913) P89LPC912_913_914_5 Product data sheet 8-bit microcontrollers with two-clock 80C51 core HIGH FREQUENCY XTAL1 MEDIUM FREQUENCY LOW FREQUENCY XTAL2 rcclk RC OSCILLATOR (7.3728 MHz 1 %) WATCHDOG OSCILLATOR (400 kHz + 30 % ...
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... NXP Semiconductors Fig 12. Block diagram of oscillator control (P89LPC914) 8.7 CCLK wake-up delay The P89LPC912/913/914 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (P89LPC912, P89LPC913) the delay is 992 OSCCLK cycles plus 100 s ...
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... NXP Semiconductors • DATA 128 B of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. • SFR Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing. • ...
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... NXP Semiconductors RTCF ERTC (RTCCON.1) WDOVF Fig 13. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC912) RTCF ERTC (RTCCON.1) WDOVF Fig 14. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC913, P89LPC914) 8.12 I/O ports The P89LPC912 and P89LPC913 devices have 4 I/O ports: Port 0, Port 1, Port 2 and Port 3 ...
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... NXP Semiconductors Table 10. Clock source On-chip oscillator or watchdog oscillator External clock input Low/medium/high-speed oscillator (external crystal or resonator) [1] Required for operation above 12 MHz. The P89LPC914 has three I/O ports: Port 0, Port 1, and Port 2. The exact number of I/O pins available depends upon the reset option chosen, as shown in Table 11 ...
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... NXP Semiconductors 8.12.3 Open-drain output configuration The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor ...
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... NXP Semiconductors 8.12.7 Additional port features After power-up, all pins are in Input-Only mode. After power-up all I/O pins except P1.5, may be configured by software. • Pin P1.5 is input only. • P1.2/T0 is configurable for either input-only or open-drain (P89LPC912, P89LPC914). Every output on the P89LPC912/913/914 has been designed to sink typical LED drive current ...
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... NXP Semiconductors 8.14.1 Idle mode Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode. 8.14.2 Power-down mode The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC912/913/914 exits Power-down mode via any reset, or certain interrupts ...
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... NXP Semiconductors Reset can be triggered from the following sources: • External reset pin (during power- user configured via UCFG1. This option must be used for an oscillator frequency above 12 MHz.) • Power-on detect • Brownout detect • Watchdog timer • Software reset • ...
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... NXP Semiconductors 8.16.4 Mode 3 When Timer Mode stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer Mode 3 it can still be used by the serial port as a baud rate generator. 8.16.5 Mode 6 (P89LPC912, P89LPC914) In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks ...
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... NXP Semiconductors 8.18.2 Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 1 overfl ...
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... NXP Semiconductors 8.18.7 Break detect Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device. 8.18.8 Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the fi ...
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... NXP Semiconductors CPU clock DIVIDER BY 4, 16, 64, 128 SPI clock master SELECT SPR1 SPR0 SPI CONTROL SPIF WCOL SPI STATUS SPI REGISTER interrupt request Fig 16. SPI block diagram (P89LPC912, P89LPC914) CPU clock DIVIDER BY 4, 16, 64, 128 SPI clock master SELECT SPR1 ...
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... NXP Semiconductors • SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e. ...
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... NXP Semiconductors Fig 19. SPI single master multiple slaves configuration Fig 20. SPI dual device configuration, where either can be a master or a slave P89LPC912_913_914_5 Product data sheet 8-bit microcontrollers with two-clock 80C51 core master MISO 8-BIT SHIFT MOSI REGISTER SPICLK SPI CLOCK ...
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... NXP Semiconductors 8.20 Analog comparators Two analog comparators are provided on the P89LPC912/913/914. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logic 1 when the positive input is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be confi ...
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... NXP Semiconductors a. CN1, OE1 = CN1, OE1 = CN2 = 0 Fig 22. Comparator configurations 8.23 Comparators and power reduction modes Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake up the processor. If the comparator output to a pin is enabled, the pin should be confi ...
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... NXP Semiconductors In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake up the CPU from Idle or Power-down modes ...
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... NXP Semiconductors 8.26 Additional features 8.26.1 Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets. 8.26.2 Dual data pointers The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions ...
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... NXP Semiconductors 8.27.4 Flash programming and erasing Different methods of erasing or programming of the flash are available. The flash may be programmed or erased in the end-user application (IAP-Lite) under control of the application’s firmware. Another option is to use the ICP mechanism. This ICP system provides for programming through a serial clock- serial data interface using a commercially available EPROM programmer which supports this device. This device does not provide for direct verifi ...
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... NXP Semiconductors 9. Limiting values Table 12. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter T bias ambient temperature amb(bias) T storage temperature stg I HIGH-level output current per OH(I/O) input/output pin I LOW-level output current per OL(I/O) input/output pin I maximum total input/output current ...
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... NXP Semiconductors 10. Static characteristics Table 13. Static characteristics 3.6 V, unless otherwise specified +85 C for industrial +125 C for extended, unless otherwise specified. amb Symbol Parameter I operating supply current DD(oper) P89LPC912, P89LPC913 P89LPC914 I Idle mode supply current DD(idle) P89LPC912, P89LPC913 P89LPC914 ...
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... NXP Semiconductors Table 13. Static characteristics 3.6 V, unless otherwise specified +85 C for industrial +125 C for extended, unless otherwise specified. amb Symbol Parameter V brownout trip voltage bo V band gap reference voltage ref(bg) TC band gap temperature bg coefficient [1] Typical ratings are not guaranteed. The values listed are at room temperature, V ...
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... NXP Semiconductors 11. Dynamic characteristics Table 14. Dynamic characteristics 3.6 V, unless otherwise specified +85 C for industrial +125 C for extended, unless otherwise specified. amb Symbol Parameter f internal RC oscillator frequency osc(RC) f internal watchdog oscillator osc(WD) frequency Crystal oscillator (P89LPC912, P89LPC913) f oscillator frequency ...
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... NXP Semiconductors Table 14. Dynamic characteristics 3.6 V, unless otherwise specified +85 C for industrial +125 C for extended, unless otherwise specified. amb Symbol Parameter t SPI enable lead time SPILEAD slave t SPI enable lag time SPILAG slave t SPICLK HIGH time SPICLKH master ...
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... NXP Semiconductors Table 15. Dynamic characteristics (P89LPC912, P89LPC913 3 3.6 V, unless otherwise specified +85 C for industrial +125 C for extended, unless otherwise specified. amb Symbol Parameter f internal RC oscillator frequency nominal osc(RC) f internal watchdog oscillator osc(WD) frequency Crystal oscillator f oscillator frequency osc T clock cycle time ...
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... NXP Semiconductors Table 15. Dynamic characteristics (P89LPC912, P89LPC913 3 3.6 V, unless otherwise specified +85 C for industrial +125 C for extended, unless otherwise specified. amb Symbol Parameter t SPI enable lead time SPILEAD slave t SPI enable lag time SPILAG slave t SPICLK HIGH time SPICLKH ...
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... NXP Semiconductors Table 15. Dynamic characteristics (P89LPC912, P89LPC913 3 3.6 V, unless otherwise specified +85 C for industrial +125 C for extended, unless otherwise specified. amb Symbol Parameter t SPI fall time SPIF SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) [1] Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down ...
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... NXP Semiconductors SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t MOSI SPIF (output) Fig 26. SPI master timing (CPHA = 0) SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t SPIF MOSI (output) Fig 27. SPI master timing (CPHA = 1) P89LPC912_913_914_5 Product data sheet 8-bit microcontrollers with two-clock 80C51 core ...
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... NXP Semiconductors SS t SPIR t SPILEAD SPICLK (CPOL = 0) (input) t SPIF SPICLK (CPOL = 1) (input) t SPIA MISO (output) t SPIDSU MOSI (input) Fig 28. SPI slave timing (CPHA = SPIR t SPILEAD SPICLK (CPOL = 0) (input) t SPIF SPICLK (CPOL = 1) (input) t SPIOH t SPIDV t SPIA MISO not defined (output) MOSI (input) Fig 29 ...
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... NXP Semiconductors 12. Other characteristics 12.1 Comparator electrical characteristics Table 16. Comparator electrical characteristics 3.6 V, unless otherwise specified +85 C for industrial +125 C for extended, unless otherwise specified. amb Symbol Parameter V input offset voltage IO V common-mode input voltage IC CMRR common-mode rejection ratio ...
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... NXP Semiconductors 13. Package outline TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Abbreviations Table 17. Acronym CRC EPROM EMI ISP LSB MSB PWM RC RTC SFR SPI UART P89LPC912_913_914_5 Product data sheet 8-bit microcontrollers with two-clock 80C51 core Acronym list Description Cyclic Redundancy Check Erasable Programmable Read-Only Memory ElectroMagnetic Interference In-System Programming Least Significant Bit Most Signifi ...
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... Figure P89LPC912_913_914_4 20070830 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added P89LPC912HDH P89LPC912_913_914-03 20041217 P89LPC912_913_914-02 20031212 ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 1 3 Product comparison . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 7 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 9 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Functional description . . . . . . . . . . . . . . . . . . 16 8.1 Special function registers . . . . . . . . . . . . . . . . 16 8 ...
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... NXP Semiconductors 9 Limiting values Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 53 11.1 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12 Other characteristics . . . . . . . . . . . . . . . . . . . . 60 12.1 Comparator electrical characteristics . . . . . . . 60 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 61 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 62 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 63 16 Legal information 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 64 16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 16.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 17 Contact information Contents ...