P89LPC912FDH NXP Semiconductors, P89LPC912FDH Datasheet - Page 49

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P89LPC912FDH

Manufacturer Part Number
P89LPC912FDH
Description
MCU 8BIT 80C51 1K FLASH, TSSOP14
Manufacturer
NXP Semiconductors
Datasheet

Specifications of P89LPC912FDH

Controller Family/series
(8051) 8052
Core Size
8bit
No. Of I/o's
12
Program Memory Size
1KB
Ram Memory Size
128Byte
Cpu Speed
18MHz
Oscillator Type
External, Internal
No. Of Timers
4
No. Of
RoHS Compliant

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NXP Semiconductors
P89LPC912_913_914_5
Product data sheet
8.27.4 Flash programming and erasing
8.27.5 In-circuit programming
8.27.6 In-application programming (IAP-Lite)
8.27.7 Using flash as data storage
8.27.8 User configuration bytes
8.27.9 User sector security bytes
Different methods of erasing or programming of the flash are available. The flash may be
programmed or erased in the end-user application (IAP-Lite) under control of the
application’s firmware. Another option is to use the ICP mechanism. This ICP system
provides for programming through a serial clock- serial data interface using a
commercially available EPROM programmer which supports this device. This device does
not provide for direct verification of code memory contents. Instead, this device provides a
32-bit CRC result on either a sector or the entire 1 kB of user code space.
ICP is performed without removing the microcontroller from the system. The ICP facility
consists of internal hardware resources to facilitate remote programming of the
P89LPC912/913/914 through a two-wire serial interface. The NXP ICP facility has made
in-circuit programming in an embedded application, using commercially available
programmers, possible with a minimum of additional expense in components and circuit
board area. The ICP function uses five pins. Only a small connector (with V
clock, and data signals) needs to be available to interface your application to a commercial
programmer in order to use this feature. Additional details may be found in the
P89LPC912/913/914 User manual .
In-Application Programming is performed in the application under the control of the
microcontroller’s firmware. The IAP-Lite facility consists of internal hardware resources to
facilitate programming and erasing. The NXP In-Application Programming Lite has made
in-application programming in an embedded application possible without additional
components. This is accomplished through the use of four SFRs consisting of a
control/status register, a data register, and two address registers. Additional details may
be found in the P89LPC912/913/914 User manual .
The flash code memory array of this device supports individual byte erasing and
programming. Any byte in the code memory array may be read using the MOVC
instruction, provided that the sector containing the byte has not been secured (a MOVC
instruction is not allowed to read code memory contents of a secured sector). Thus any
byte in a non-secured sector may be used for non-volatile data storage.
Some user-configurable features of the P89LPC912/913/914 must be defined at power-up
and therefore cannot be set by the program after start of execution. These features are
configured through the use of the flash byte UCFG1. Please see the P89LPC912/913/914
User manual for additional details.
There are four User Sector Security Bytes, each corresponding to one sector. Please see
the P89LPC912/913/914 User manual for additional details.
Rev. 05 — 28 September 2007
8-bit microcontrollers with two-clock 80C51 core
P89LPC912/913/914
© NXP B.V. 2007. All rights reserved.
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