P89LPC912FDH NXP Semiconductors, P89LPC912FDH Datasheet - Page 32

• Manufacturer Part Number: P89LPC912FDH
• Description: MCU 8BIT 80C51 1K FLASH, TSSOP14
• Manufacturer: NXP Semiconductors

Specifications of P89LPC912FDH

• Controller Family/series: (8051) 8052
• Core Size: 8bit
• No. Of I/o's: 12
• Program Memory Size: 1KB
• Ram Memory Size: 128Byte
• Cpu Speed: 18MHz
• Oscillator Type: External, Internal
• No. Of Timers: 4
• No. Of: RoHS Compliant

NXP Semiconductors
P89LPC912_913_914_5
Product data sheet
8.11.1 External interrupt inputs
8.11 Interrupts
The P89LPC912/913/914 uses a four priority level interrupt structure. This allows great
flexibility in controlling the handling of the many interrupt sources.
The P89LPC912 supports 7 interrupt sources: timers 0 and 1, brownout detect,
Watchdog/Real-Time clock, keyboard, comparators 1 and 2, and SPI.
The P89LPC913 and P89LPC914 devices support 10 interrupt sources: timers 0 and 1,
serial port TX, serial port RX, combined serial port RX/TX, brownout detect,
Watchdog/Real-Time clock, keyboard, comparators 1 and 2, and SPI.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in
the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global
disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt, but
not by another interrupt of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. If two requests of different priority
levels are pending at the start of an instruction, the request of higher priority level is
serviced.
If requests of the same priority level are pending at the start of an instruction, an internal
polling sequence determines which request is serviced. This is called the arbitration
ranking. Note that the arbitration ranking is only used to resolve pending requests of the
same priority level.
The P89LPC912/913/914 has a Keypad Interrupt function. This can be used as an
external interrupt input.
If enabled when the P89LPC912/913/914 is put into Power-down or Idle mode, the
interrupt will cause the processor to wake-up and resume operation. Refer to
“Power reduction modes”
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DATA
128 B of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area.
SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing.
CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC912/913/914 has 1 kB of on-chip Code memory.
Rev. 05 — 28 September 2007
for details.
8-bit microcontrollers with two-clock 80C51 core
P89LPC912/913/914
© NXP B.V. 2007. All rights reserved.
Section 8.14
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