PIC16F628AT-E/SS Microchip Technology, PIC16F628AT-E/SS Datasheet - Page 112

• Manufacturer Part Number: PIC16F628AT-E/SS
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F628AT-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DBF648 - BOARD DAUGHTER ICEPIC3AC162053 - HEADER INTERFACE ICD,ICD2 18DIP
• Data Converters: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F627A/628A/648A
FIGURE 14-16:
TABLE 14-9:
14.8
The Power-down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the Status register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before SLEEP was executed (driving high, low or high-
impedance).
DS40044G-page 112
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.
81h, 181h
Address
2007h
Note:
Note:
Power-Down Mode (Sleep)
Shaded cells are not used by the Watchdog Timer.
CONFIG
OPTION
Name
T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
SUMMARY OF WATCHDOG TIMER REGISTERS
Enable Bit
Watchdog
WATCHDOG TIMER BLOCK DIAGRAM
RBPU INTEDG
Bit 7
LVP
Timer
WDT
From TMR0 Clock Source
BOREN MCLRE FOSC2
(Figure 6-1)
Bit 6
T0CS
Bit 5
PSA
0
1
M
U
X
T0SE
Bit 4
PWRTE
Bit 3
PSA
For lowest current consumption in this mode, all I/O
pins should be either at V
circuitry drawing current from the I/O pin and the
comparators, and V
that are high-impedance inputs should be pulled high
or low externally to avoid switching currents caused by
floating inputs. The T0CKI input should also be at V
or
contribution from on chip pull-ups on PORTB should be
considered.
The MCLR pin must be at a logic high level (V
0
WDT Postscaler/
TMR0 Prescaler
Time-out
Note:
MUX
WDT
WDTE
Bit 2
V
8 to 1 MUX
PS2
SS
1
8
for
It should be noted that a Reset generated
by a WDT time-out does not drive MCLR
pin low.
FOSC1
Bit 1
PS1
lowest
PSA
3
(Figure 6-1)
REF
PS<2:0>
To TMR0
FOSC0 uuuu uuuu uuuu uuuu
Bit 0
PS0
© 2009 Microchip Technology Inc.
current
should be disabled. I/O pins
DD
1111 1111 1111 1111
or V
POR Reset
Value on
consumption.
SS
with no external
Value on
all other
Resets
IHMC
The
).
DD