PIC16F628AT-E/SS Microchip Technology, PIC16F628AT-E/SS Datasheet - Page 20

• Manufacturer Part Number: PIC16F628AT-E/SS
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F628AT-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DBF648 - BOARD DAUGHTER ICEPIC3AC162053 - HEADER INTERFACE ICD,ICD2 18DIP
• Data Converters: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F627A/628A/648A
4.2.2
The SFRs are registers used by the CPU and Periph-
eral functions for controlling the desired operation of
the device (Table 4-3). These registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The SFRs associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section of that peripheral feature.
TABLE 4-3:
DS40044G-page 20
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend:
Note
Address
1:
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CMCON
For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.
SPECIAL FUNCTION REGISTERS
- = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Name
—
—
—
—
—
—
—
—
—
—
SPECIAL REGISTERS SUMMARY BANK0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s Register
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR2 Module’s Register
Unimplemented
Unimplemented
Capture/Compare/PWM Register (LSB)
Capture/Compare/PWM Register (MSB)
USART Transmit Data Register
USART Receive Data Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
C2OUT
SPEN
EEIF
Bit 7
RA7
RB7
IRP
GIE
—
—
—
—
TOUTPS3
C1OUT
CMIF
PEIE
Bit 6
RP1
RA6
RB6
RX9
—
—
—
T1CKPS1
TOUTPS2 TOUTPS1
CCP1X
C2INV
SREN
RCIF
Bit 5
T0IE
RP0
RA5
RB5
—
Write Buffer for upper 5 bits of Program Counter
T1CKPS0
CCP1Y
CREN
C1INV
Bit 4
INTE
TXIF
RA4
RB4
TO
T1OSCEN
TOUTPS0
CCP1M3
ADEN
RBIE
Bit 3
RA3
RB3
CIS
PD
—
TMR2ON
CCP1M2
T1SYNC
CCP1IF
FERR
Bit 2
CM2
RA2
RB2
T0IF
Z
T2CKPS1
TMR1CS
CCP1M1
TMR2IF
OERR
Bit 1
INTF
CM1
RA1
RB1
DC
© 2009 Microchip Technology Inc.
T2CKPS0 -000 0000
TMR1ON
CCP1M0
TMR1IF
RX9D
RBIF
Bit 0
CM0
RA0
RB0
C
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
xxxx 0000
xxxx xxxx
---0 0000
0000 000x
0000 -000
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 000x
0000 0000
0000 0000
0000 0000
Value on
Reset
POR
—
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—
—
—
—
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