PIC16F628AT-E/SS Microchip Technology, PIC16F628AT-E/SS Datasheet - Page 73

• Manufacturer Part Number: PIC16F628AT-E/SS
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F628AT-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DBF648 - BOARD DAUGHTER ICEPIC3AC162053 - HEADER INTERFACE ICD,ICD2 18DIP
• Data Converters: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.0
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) is also known as a Serial
Communications Interface (SCI). The USART can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices such as CRT
terminals and personal computers, or it can be
configured as a half-duplex synchronous system that
can communicate with peripheral devices such as A/D
or D/A integrated circuits, Serial EEPROMs, etc.
REGISTER 12-1:
© 2009 Microchip Technology Inc.
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
MODULE
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TXSTA – TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS: 98h)
bit 7
CSRC: Clock Source Select bit
Asynchronous mode
Synchronous mode
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
Unimplemented: Read as ‘0’
BRGH: High Baud Rate Select bit
Asynchronous mode
Synchronous mode
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
TX9D: 9th bit of transmit data. Can be parity bit.
Legend:
R = Readable bit
-n = Value at POR
R/W-0
CSRC
Note 1: SREN/CREN overrides TXEN in SYNC mode.
1 = High speed
0 = Low speed
Unused in this mode
Don’t care
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
R/W-0
TX9
R/W-0
TXEN
(1)
W = Writable bit
‘1’ = Bit is set
PIC16F627A/628A/648A
R/W-0
SYNC
The USART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous
• Synchronous
Bit SPEN (RCSTA<7>) and bits TRISB<2:1> have to be
set in order to configure pins RB2/TX/CK and RB1/RX/DT
as the Universal Synchronous Asynchronous Receiver
Transmitter.
Register 12-1 shows the Transmit Status and Control
Register (TXSTA) and Register 12-2 shows the
Receive Status and Control Register (RCSTA).
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
–
–
Master (half-duplex)
Slave (half-duplex)
R/W-0
BRGH
x = Bit is unknown
TRMT
R-1
DS40044G-page 73
R/W-0
TX9D
bit 0