PIC16F628AT-E/SS Microchip Technology, PIC16F628AT-E/SS Datasheet - Page 90

• Manufacturer Part Number: PIC16F628AT-E/SS
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F628AT-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DBF648 - BOARD DAUGHTER ICEPIC3AC162053 - HEADER INTERFACE ICD,ICD2 18DIP
• Data Converters: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F627A/628A/648A
12.5.2
The operation of the Synchronous Master and Slave
modes is identical except in the case of the Sleep
mode. Also, bit SREN is a “don’t care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
TABLE 12-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
DS40044G-page 90
Legend:
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave reception.
Address
Address
0Ch
8Ch
0Ch
1Ah
8Ch
18h
19h
98h
99h
18h
98h
99h
TXREG USART Transmit Data Register
SPBRG Baud Rate Generator Register
RCREG USART Receive Data Register
SPBRG Baud Rate Generator Register
RCSTA
TXSTA
RCSTA
TXSTA
USART SYNCHRONOUS SLAVE
RECEPTION
Name
Name
PIR1
PIE1
PIR1
PIE1
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave transmission.
SPEN
CSRC
CSRC
SPEN
Bit 7
EEIF
EEIE
EEIF
EEIE
Bit 7
CMIF
CMIE
CMIE
Bit 6
CMIF
RX9
Bit 6
TX9
RX9
TX9
SREN CREN
TXEN SYNC
SREN CREN
TXEN SYNC
RCIF
RCIE
Bit 5
RCIF
RCIE
Bit 5
Bit 4
TXIF
TXIE
Bit 4
TXIF
TXIE
ADEN
ADEN
Bit 3
Bit 3
—
—
—
—
—
—
CCP1IF TMR2IF TMR1IF 0000 -000
CCP1IE TMR2IE TMR1IE 0000 -000
CCP1IF TMR2IF TMR1IF 0000 -000
CCP1IE TMR2IE TMR1IE 0000 -000
BRGH
FERR
BRGH
FERR
Follow these steps when setting up a Synchronous
Slave Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Bit 2
Bit 2
TRISB<1> and TRISB<2> should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated, if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If an OERR error occurred, clear the error by
clearing bit CREN.
OERR
TRMT
OERR
TRMT
Bit 1
Bit 1
RX9D
TX9D
RX9D
TX9D
Bit 0
Bit 0
© 2009 Microchip Technology Inc.
0000 000x
0000 0000
0000 -010
0000 0000
0000 000x
0000 0000
0000 -010
0000 0000
Value on
Value on
POR
POR
other Resets
other Resets
Value on all
0000 -000
0000 000x
0000 0000
0000 -000
0000 -010
0000 0000
Value on all
0000 -000
0000 000x
0000 0000
0000 -000
0000 -010
0000 0000