QLX4600SIQSR Intersil, QLX4600SIQSR Datasheet - Page 16

• Manufacturer Part Number: QLX4600SIQSR
• Description: IC EQUALIZER REC 6.25GBPS 46QFN
• Manufacturer: Intersil

Specifications of QLX4600SIQSR

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Bus Programming
Pins 16 (DI), 45 (ENB), and 46 (CLK) are used to
program the registers inside the QLx4600-S30. Figure 27
shows an exemplary timing diagram for the signals on
these pins. The serial bus can be used to program a
single QLx4600-S30 according to the following steps:
1. The ENB pin is pulled ‘LOW’.
2. At least 21 values are read from DI on the rising
REGISTER
- While this pin is ‘LOW’, the data input on DI are
- A setup time of t
- If more than 21 values are passed in, then only the
- The data on DI should start by sending the value
- A range of clock frequencies can be used. A typical
- Setup (t
edge of the CLK signal.
read into registers but not yet latched.
‘LOW’ and the first rising clock edge.
last 21 values are kept in a FIFO fashion.
destined for register 21 and finish by sending the
value destined for register 1.
rate is 10MHz. The clock should not exceed 20MHz.
around the rising clock edge.
10
11
12
13
14
15
16
17
18
19
20
21
1
2
3
4
5
6
7
8
9
SDI
EQUALIZER CHANNEL
) and hold (t
SCK
1-4
16
is needed between ENB going
1
2
3
4
HDI
TABLE 4. DESCRIPTION OF INTERNAL SERIAL REGISTERS
) times are needed
CP control override – Use registers 2 through 21 (rather than CP pins) to establish
the boost levels when this bit is set.
Equalizer setting bit 0 (LSB).
Equalizer setting bit 1.
Equalizer setting bit 2.
Equalizer setting bit 3.
Equalizer setting bit 4 (MSB).
Equalizer setting bit 0 (LSB).
Equalizer setting bit 1.
Equalizer setting bit 2.
Equalizer setting bit 3.
Equalizer setting bit 4 (MSB).
Equalizer setting bit 0 (LSB).
Equalizer setting bit 1.
Equalizer setting bit 2.
Equalizer setting bit 3.
Equalizer setting bit 4 (MSB).
Equalizer setting bit 0 (LSB).
Equalizer setting bit 1.
Equalizer setting bit 2.
Equalizer setting bit 3.
Equalizer setting bit 4 (MSB).
QLx4600-S30
3. The ENB pin is pulled ‘HIGH’ and the contents of the
- After clocking in the last data bit, an additional
- After completing these steps, the new values will
registers are latched and take effect.
t
‘HIGH’.
affect within t
HEN
should elapse before pulling the ENB signal
DESCRIPTION
D
.
November 19, 2009
FN6979.1