QLX4600SIQSR Intersil, QLX4600SIQSR Datasheet - Page 17

• Manufacturer Part Number: QLX4600SIQSR
• Description: IC EQUALIZER REC 6.25GBPS 46QFN
• Manufacturer: Intersil

Specifications of QLX4600SIQSR

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programming Multiple QLx4600-S30
Devices
The serial bus interface provides a simple means of
setting the equalizer boost levels with a minimal amount
of board circuitry. Many of the serial interface signals can
be shared among the QLx4600-S30 devices on a board
and two options are presented in this section. The first
uses common clock and serial data signals along with
separate ENB signals to select which QLx4600-S30
accepts the programmed changes. The second method
uses a common ENB signal as the serial data is
carried-over from one QLx4600-S30 to the next.
Separate ENB Signals
Multiple QLx4600-S30 devices can be programmed from
a common serial data stream as shown in Figure 28.
Here, each QLx4600-S30 is provided its own ENB signal,
and only one of these ENB signals is pulled ‘LOW’, and
hence accepting the register data, at a time. In this
situation, the programming of each equalizer follows the
steps outlined in Figure 29.
FIGURE 28. SERIAL BUS PROGRAMMING MULTIPLE QLx4600-S30 DEVICES USING SEPARATE ENB SIGNALS
Register
FIGURE 27. TIMING DIAGRAM FOR PROGRAMMING THE INTERNAL REGISTERS OF THE QLx4600-S30
Serial
Clock
Data
ENB (A)
ENB
CLK
DI
ENB
CLK
QLx4600-S30
17
(A)
t
SCK
DO
DI
R21
ENB (B)
t
SDI
R20
t
HDI
ENB
CLK
QLx4600-S30
QLx4600-S30
R19
(B)
DO
DI
DI/DO Carryover
The DO pin (pin 17) can be used to daisy-chain the serial
bus among multiple QLx4600-S30 chips. The DO pin
outputs the overflow data from the DI pin. Specifically, as
data is pipelined into a QLx4600-S30, it proceeds
according to the following flow. First, a bit goes into
shadow register 1. Then, with each clock cycle, it shifts
over into subsequent higher numbered registers. After
shifting into register 21, it is output on the DO pin on the
same clock cycle. Thus, the DO signal is equal to the DI
signal, but delayed by 20 clock cycles. The timing
diagram for the DO pin is shown in Figure 27 where the
first 20 bits output from the DO are indefinite and
subsequent bits are the data fed into the DI pin. The
delay between the rising clock edge and the data
transition is t
A diagram for programming multiple QLx4600-S30s is
shown in Figure 30. It is noted that the board layout
should ensure that the additional clock delay experienced
between subsequent QLx4600-S30s should be no more
than the minimum value of t
ENB (C)
ENB
CLK
QLx4600-S30
CQ
.
(C)
DO
DI
R1
ENB (D)
CQ
t
HEN
, i.e. 12ns.
ENB
CLK
QLx4600-S30
(D)
November 19, 2009
DO
DI
FN6979.1