XAUI-PM-U1 Lattice, XAUI-PM-U1 Datasheet

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... Lever TM CORE CORE XAUI IP Core User’s Guide November 2009 ipug68_01.3 ...

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... General Description XAUI is a high-speed interconnect that offers reduced pin count and has the ability to drive inches of PCB trace on standard FR-4 material. Each XAUI interface comprises four self-timed 8b10b encoded serial lanes each operating at 3 ...

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... Lattice Semiconductor Figure 1. XAUI and XGXS Locations in 10 GbE Protocol Stack MAC Control (Optional) Media Access Control (MAC) XGMII XAUI XGMII Physical Coding Sublayer (PCS) WAN Interface Sublayer (WIS)* XSBI Physical Medium Attachment (PMA) Physical Medium Dependent (PMD) MDI Figure 2. XAUI Solution Simplified Block Diagram ...

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... Lattice Semiconductor Figure 3. XAUI IP Core I/O reset_n clk_156_tx If TX Slip Buffer is selected clk_156_rx If RX Slip Buffer is selected clk_156_asb_tx clk_156_asb_rx rwdata_lane0 rwdata_lane1 rwdata_lane2 rwdata_lane3 rcomma_lane0 rcomma_lane1 rcomma_lane2 rcomma_lane3 tx_data tx_ctrl mca_resync If MDIO is NOT selected mdin mdc scireaddata If MDIO is selected gpi XAUI IP Core User’s Guide ...

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... I 156MHz XGMII TX clock I 156MHz XGMII RX clock I XAUI multi-channel alignment resynchronization request XAUI multi-channel alignment status All XAUI channels are aligned 0 = XAUI channels are not aligned I MDIO serial input data I MDIO input clock O MDIO serial output data O Tristate control for MDIO port ...

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... Include MDIO Functional Description The XAUI receive path, shown in Figure 4, is the data path from the XAUI to the XGMII interface. In the receive direction, 8b10b encoded data received at the XAUI SERDES interface is demultiplexed and passed to the multi- channel alignment block, that compensates for lane-to-lane skew between the four SERDES channels as specified in 802 ...

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... Lattice Semiconductor Figure 4. XAUI IP Core Receive Path With Optional Receive Direction Slip Buffer FPGA xgmii_txclk_156 clk_156_rx xgmii_txclk_156_out 90° PLL xgmii_tx_data[31:0] XGMII TX xgmii_tx_ctrl[3:0] DDR Output Without Optional Receive Direction Slip Buffer FPGA xgmii_txclk_156_out 90° PLL xgmii_tx_data[31:0] XGMII TX xgmii_tx_ctrl[3:0] DDR Output XAUI IP CORE ...

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... The transmit path, shown in Figure 6, is the data path from XGMII to XAUI. In the transmit direction, the 36-bit DDR data and control received at the XGMII are converted to single-edge timing and passed through an optional slip buffer that compensates for XAUI and XGMII timing differences. The XGMII data and control are then passed to the TX encoder, where they are translated and mapped to the 8b10b XAUI transmission code and then passed to the SERDES interface ...

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... Lattice Semiconductor Figure 6. XAUI IP Core Transmit Path With Optional Transmit Direction Slip Buffer FPGA xgmii_rxclk_156 PLL xgmii_rx_data[31:0] XGMII RX xgmii_rx_ctrl[3:0] DDR Input Without Optional Transmit Direction Slip Buffer FPGA xgmii_rxclk_156 PLL xgmii_rx_data[31:0] XGMII RX xgmii_rx_ctrl[3:0] DDR Input XAUI IP CORE clk_156_tx tx_ddr_clk 72b @ 72b @ ...

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... XAUI Lane 0 XGMII and Slip Buffers The 10Gigabit Media Independent Interface (XGMII) supported by the XAUI IP core solution conforms to Clause 46 of IEEE 802.3ae.The XGMII is composed of independent transmit and receive paths. Each direction uses 32 data signals, four control signals and a clock. The 32 data signals in each direction are organized into four lanes of eight signals each ...

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... XAUI stream into XGMII-compatible signals. At the embedded core interface, the IP core receive block receives 72 bits of data at 156 MHz (64 bits of data, 8 bits of control) from four XAUI lanes. Data from the embedded core are first passed to the RX multi-channel aligner block to de-skew the four XAUI lanes. ...

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... K28.4 (0x9C) XGMII-to-XAUI Translation (Transmit Interface) A block diagram of the XAUI IP core transmit data path was shown previously in Figure 6. The TX interface con- verts the incoming XGMII data into XAUI-compatible characters. 36-bit XGMII DDR input data and control signals are initially converted to a 72-bit bus based on a single edge 156MHz clock. The data and control read are then passed into an optional TX slip buffer identical to the one used for the RX interface ...

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... Figure 8). The idle generation state machine specified in IEEE 802.3ae and shown in Figure 7 transitions between states based on a 312 MHz system clock. The TX encoder implemented in the XAUI IP runs at a system clock rate of 156 MHz. Thus the XGXS state machine implementation performs the equivalent of two state transitions each clock cycle. ...

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... The TA field (Turn Around 2-bit turnaround time spacing between the device address field and the data field to avoid contention during a read transaction. The TA bits are treated as don’t cares by the XAUI core. During a write or address operation, the address/data field transports 16 bits of write data or register address depending on the access type ...

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... XGXS registers implemented in the programmable array. All corresponding registers are listed in Table 9. All PCS embedded core registers can be accessed thru the 4.9xxxh registers shown in Table 10, where the address is directly mapped to the PCS embedded registers. Register Descriptions Table 8. Register Map for XAUI IP Core (Device Address = 4) Register Address 32768 - 65535 Table 9. XAUI IP Core Registers ...

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... Lattice Semiconductor Table 9. XAUI IP Core Registers (Continued) Bit(s) Name 4.0.[1:0] Reserved Status 1 Register 4.1.[15:8] Reserved 4.1.7 Fault (not supported Fault condition 4.1.[6:3] Reserved 4.1.2 PHY XS TX link sta- tus (not supported) 4.1.1 Low Power Ability 4.1.0 Reserved XGXS Identifier Registers 4 ...

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... Lattice Semiconductor Table 9. XAUI IP Core Registers (Continued) Bit(s) Name 4.24.2 Lane 2 Sync (not supported) 4.24.1 Lane 1 Sync (not supported) 4.24.0 Lane 0 Sync (not supported) 4.25.15:3 Reserved 4.25.2 Receive test pattern enable 4.25.1:0 Test pattern select 4.8000.[15:0] MCA Sync Request 4.8001.15 MCA Sync Status 4 ...

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... 1. 0.75V REF t t pwmi pwmi hold Symbol Driver Receiver t 960 480 SETUP t 960 480 HOLD t 2.5 - PWMIN 18 XAUI IP Core User’s Guide Max. 1.8 0.9 - VDDIO + 0.3 VREF - 100mV - - 0 Ω V IH_AC(min) V IL_AC(max) V IH_AC(min) V IL_AC(max) t setup t hold Units Units ...

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... MDIO (O) hold time from MDC rising edge t6 MDIO (O) valid from MDC rising edge Core Generation The XAUI IP is available for download from the Lattice website at www.latticesemi.com/ip. The IP files are automat- ically installed using ispUPDATE technology in any user-specified directory. ® The ispLEVER IPexpress™ ...

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... Lattice Semiconductor Figure 14. IPexpress GUI Window To create a custom configuration, click on the Customize button to display the XAUI IP core Configuration GUI, shown in Figure 15. From this window the user may select the appropriate parameters. XAUI IP Core User’s Guide 20 ...

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... Figure 15. XAUI IP Configuration GUI Window When the user clicks the Generate button, the configuration-specific IP core and supporting files are generated in the user’s project directory. The directory structure of the generated files is shown in Figure 16. Figure 16. XAUI IP Core Generated Directory Structure XAUI IP Core User’s Guide 21 ...

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... IP core configuration username. These are all of the files needed by the user to implement and verify the XAUI IP core in their top-level design. The following additional files providing IP core generation status information and command line generation capability are generated in the user’ ...

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... Copy and paste the instance template (<username>_inst.v) into the user netlist where the XAUI IP core resides (not limited to user’s top level). • Edit the connection list as necessary to connect the XAUI IP core to the rest of the user design. • Run the synthesis tool, making sure the component definition file (<username>_bb.v) is included in the list of files to be compiled. The resulting netlist will contain a black box instantiation of the XAUI IP core. • ...

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... June 2009 November 2009 Version 01.0 Initial release. 01.1 Title changed from “10Gb Ethernet Attachment Unit Interface (XAUI) IP Core User’s Guide” to “XAUI IP Core User’s Guide”. Updated Appendix for LatticeECP2M FPGAs. 01.2 Added support for LatticeECP3 FPGA family. 01.3 Updated utilization tables with ispLEVER 8 ...

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... Ordering Part Number The Ordering Part Number (OPN) for all configurations of the XAUI IP core targeting LatticeECP2M/S devices is XAUI-PM-U1. IPexpress is the Lattice IP configuration utility, and is included as a standard feature of the ispLEVER design tools. Details regarding the usage of IPexpress can be found in the IPexpress and ispLEVER help system. For more infor- mation on the ispLEVER design tools, visit the Lattice web site at: www ...

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... LatticeECP3 family different software version, resource utilization may vary. Ordering Part Number The Ordering Part Number (OPN) for the XAUI IP core targeting LatticeECP3 devices is XAUI-E3-U1. IPexpress is the Lattice IP configuration utility, and is included as a standard feature of the ispLEVER design tools. ...