XAUI-PM-U1 Lattice, XAUI-PM-U1 Datasheet - Page 5

• Manufacturer Part Number: XAUI-PM-U1
• Description: Development Software XAUI 10Gb Ethernet
• Manufacturer: Lattice

Specifications of XAUI-PM-U1

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 1. IP Core I/O and Signal Definitions
XAUI IP Core I/O
Table 1 defines all I/O interface ports available in this core.
All Configurations
reset_n
clk_156_asb_tx
clk_156_asb_rx
rwdata_lane0
rwdata_lane1
rwdata_lane2
rwdata_lane3
rcomma_lane0
rcomma_lane1
rcomma_lane2
rcomma_lane3
twdata_lane0
twdata_lane1
twdata_lane2
twdata_lane3
tcomma_lane0
tcomma_lane1
tcomma_lane2
tcomma_lane3
rx_ddr_clk
tx_ddr_clk
tx_data
tx_ctrl
rx_data
rx_ctrl
With Optional RX Slip Buffer
clk_156_rx
With Optional TX Slip Buffer
clk_156_tx
No MDIO Option
mca_resync
mca_sync_status
MDIO Option
mdin
mdc
mdout
mdtri
scireaddata
sciwritedata
Name
Width (Bits) Direction
16
16
16
16
16
16
16
16
64
64
1
1
1
2
2
2
2
2
2
2
2
1
1
8
8
1
1
1
1
1
1
1
1
8
8
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Active-low asynchronous reset
156MHz XAUI transmit clock (from PCS)
156MHz XAUI receive clock (from PCS)
XAUI receive data channel 0 (from PCS)
XAUI receive data channel 1 (from PCS)
XAUI receive data channel 2 (from PCS)
XAUI receive data channel 3 (from PCS)
XAUI receive control channel 0 (from PCS)
XAUI receive control channel 1 (from PCS)
XAUI receive control channel 2 (from PCS)
XAUI receive control channel 3 (from PCS)
XAUI transmit data channel 0 (to PCS)
XAUI transmit data channel 1 (to PCS)
XAUI transmit data channel 2 (to PCS)
XAUI transmit data channel 3 (to PCS)
XAUI transmit control channel 0 (to PCS)
XAUI transmit control channel 1 (to PCS)
XAUI transmit control channel 2 (to PCS)
XAUI transmit control channel 3 (to PCS)
DDR clock from IP Core to the XGMII TX direction
DDR clock from IP Core to the XGMII receive direction
IP Core transmit data from XGMII RX
IP Core transmit control from XGMII RX
Receive data from core and sent to XGMII TX
Receive control from core and sent to XGMII TX
156MHz XGMII TX clock
156MHz XGMII RX clock
XAUI multi-channel alignment resynchronization request
XAUI multi-channel alignment status.
1 = All XAUI channels are aligned 0 = XAUI channels are not aligned
MDIO serial input data
MDIO input clock
MDIO serial output data
Tristate control for MDIO port
SCI read data (from PCS)
SCI write data (to PCS)
5
Description
XAUI IP Core User’s Guide