XAUI-PM-U1 Lattice, XAUI-PM-U1 Datasheet - Page 8

• Manufacturer Part Number: XAUI-PM-U1
• Description: Development Software XAUI 10Gb Ethernet
• Manufacturer: Lattice

Specifications of XAUI-PM-U1

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 5. XAUI IP Core Receive Direction Data Translations
The transmit path, shown in Figure 6, is the data path from XGMII to XAUI. In the transmit direction, the 36-bit DDR
data and control received at the XGMII are converted to single-edge timing and passed through an optional slip
buffer that compensates for XAUI and XGMII timing differences. The XGMII data and control are then passed to the
TX encoder, where they are translated and mapped to the 8b10b XAUI transmission code and then passed to the
SERDES interface.
The transmit direction data translations are shown in Figure 7. Data and control from each of the four XGMII lanes
are translated and mapped to the corresponding XAUI lanes. The transmit encoder includes the transmit idle gen-
eration state machine that generates a random sequence of /A/, /K/ and /R/ code groups as specified in IEEE
802.3ae.
a
0 0 1 1 1 1 1 X X X
b c d e i f g
K A B C D E F G H
C 0 1 2 3 4 5 6 7
xgmii_tx_data[7:0]
XAUI Lane 0
xgmii_tx_ctrl[0]
10b8b decoding
XGXS mapping
h j
xgmii_tx_data[15:8]
xgmii_tx_ctrl[1]
properly aligned comma
Lane 1
XGMII
8
xgmii_tx_data[23:16]
xgmii_tx_ctrl[2]
XGXS Receive Function
Lane 2
xgmii_tx_data[31:24]
XAUI IP Core User’s Guide
xgmii_tx_ctrl[3]
Lane 3