XAUI-PM-U1 Lattice, XAUI-PM-U1 Datasheet - Page 23

• Manufacturer Part Number: XAUI-PM-U1
• Description: Development Software XAUI 10Gb Ethernet
• Manufacturer: Lattice

Specifications of XAUI-PM-U1

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Synthesizing and Implementing the Core in a Top-Level Design
As mentioned previously, the XAUI IP core itself is synthesized and is provided in NGO format when the core is
generated. Users may include the core in their own top-level design by instantiating the core in their top-level and
then synthesizing the entire design with either Synplify
The following steps are used in the implementation phase of the design process:
• Copy and paste the instance template (<username>_inst.v) into the user netlist where the XAUI IP core resides
• Edit the connection list as necessary to connect the XAUI IP core to the rest of the user design.
• Run the synthesis tool, making sure the component definition file (<username>_bb.v) is included in the list of
• When running map, place, and route, make sure the <username>.ngo and associated pmi_*.ngo memory files
Implementation Evaluation
An example RTL top-level reference source file supporting XAUI core top-level synthesis and implementation is
provided with the IP core in \<project_dir>\xaui_core_eval\<username>\src\rtl\top.
Push-button implementation of this design is supported via an ispLEVER project file <username>_eval.syn located
in \<project_dir>\xaui_core_eval\<username>\impl. To use this project file:
1. Select Open Project under the File tab in ispLEVER.
2. Browse to \<project_dir>\xaui_core_eval\<username>\impl in the Open Project dialog box.
3. Select and open <username>_eval.syn. A this point, all of the files needed to support top-level synthesis and
4. Select the device top-level entry in the left-hand GUI window.
5. Implement the complete design via the standard ispLEVER GUI flow.
Hardware Evaluation
Lattice’s IP hardware evaluation capability makes it possible to create versions of IP cores that operate in hardware
for a limited period of time (approximately four hours) without requiring the purchase on an IP license. The hard-
ware evaluation capability is turned on by enabling the Hardware Evaluation option in the properties of the Build
Database process in ispLEVER. When the Hardware Evaluation option is enabled it is possible to generate a pro-
gramming file that may be downloaded into the device. After initialization, the IP core will be operational for approx-
imately four hours. After four hours, the IP core will stop working and it will be necessary to reprogram the device to
re-enable operation. This hardware evaluation capability is only enabled if the core has not been licensed. If a
license is detected, core generation is completed with no restrictions.
References
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(not limited to user’s top level).
files to be compiled. The resulting netlist will contain a black box instantiation of the XAUI IP core.
can be found by the ispLEVER software. This is accomplished either by copying the <username>.ngo file to the
place-and-route working directory, or pointing to the directory where it resides.
FPGA Design with ispLEVER Tutorial
ispLeverCORE IP Module Evaluation Tutorial
implementation will be imported to the project.
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or Precision
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RTL Synthesis.
XAUI IP Core User’s Guide