XAUI-PM-U1 Lattice, XAUI-PM-U1 Datasheet - Page 2

• Manufacturer Part Number: XAUI-PM-U1
• Description: Development Software XAUI 10Gb Ethernet
• Manufacturer: Lattice

Specifications of XAUI-PM-U1

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Introduction
The 10Gb Ethernet Attachment Unit Interface (XAUI) IP Core User’s Guide for the LatticeECP2M™ and
LatticeECP3™ FPGAs provides a solution for bridging between XAUI and 10-Gigabit Media Independent Interface
(XGMII) devices. This user’s guide implements 10Gb Ethernet Extended Sublayer (XGXS) capabilities in soft logic
that together with PCS and SERDES functions implemented in the FGPA provides a complete XAUI-to-XGMII solu-
tion.
The XAUI IP core package comes with the following documentation and files:
• Protected netlist/database
• Behavioral RTL simulation model
• Source files for instantiating and evaluating the core
The XAUI IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of
the IP core that operate in hardware for a limited period of time (approximately four hours) without requiring the pur-
chase on an IP license. It may also be used to evaluate the core in hardware in user-defined designs. Details for
using the hardware evaluation capability are described in the Hardware Evaluation section of this document.
Features
• XAUI compliant functionality supported by embedded SERDES PCS functionality implemented in the
• Complete 10Gb Ethernet Extended Sublayer (XGXS) solution based on LatticeECP2M and LatticeECP3 FPGA.
• Soft IP targeted to the FPGA implements XGXS functionality conforming to IEEE 802.3ae-2002, including:
• ModelSim
General Description
XAUI is a high-speed interconnect that offers reduced pin count and has the ability to drive up to 20 inches of PCB
trace on standard FR-4 material. Each XAUI interface comprises four self-timed 8b10b encoded serial lanes each
operating at 3.125 Gbps and thus is capable of transferring data at an aggregate rate of 10 Gbps.
XGMII is a 156 MHz Double Data Rate (DDR), parallel, short-reach interconnect interface (typically less than 2
inches). It supports interfacing to 10 Gbps Ethernet Media Access Control (MAC) and PHY devices.
The locations of XAUI and XGXS in the 10GbE protocol stack are shown in Figure 1. A simplified block diagram of
the XAUI solution is shown in Figure 2. The XGMII interface, XGXS coding and state machines and XAUI multi-
channel alignment capabilities are implemented in the FPGA array. The XAUI 8b10b coding and SERDES function-
ality are supported by the embedded SERDES_PCS block. An optional MDIO interface module is also
implemented in the FPGA array.
Figure 3 shows the I/O interface view of the XAUI IP core.
LatticeECP2M and LatticeECP3, including four channels of 3.125 Gbps serializer/deserializer with 8b10b encod-
ing/decoding.
– 10 GbE Media Independent Interface (XGMII).
– Optional Slip buffers for clock domain transfer to/from the XGMII interface.
– Complete translation between XGMII and XAUI PCS layers, including 8b10b encoding and decoding of Idle,
– XAUI compliant lane-by-lane synchronization.
– Lane deskew functionality.
– Interface with the high-speed SERDES block embedded in the LatticeECP2M and LatticeECP3 that imple-
– Optional standard compliant MDIO/MDC interface.
Start, Terminate, Error and Sequence code groups and sequences, and randomized Idle generation in the
XAUI transmit direction.
ments a standard XAUI.
®
simulation models and test benches provided for free evaluation.
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XAUI IP Core User’s Guide