XAUI-PM-U1 Lattice, XAUI-PM-U1 Datasheet - Page 15

• Manufacturer Part Number: XAUI-PM-U1
• Description: Development Software XAUI 10Gb Ethernet
• Manufacturer: Lattice

Specifications of XAUI-PM-U1

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
For an address cycle, this field contains the address of the register to be accessed on the next cycle. For
read/write/increment cycles, the field contains the data for the register. The first bit of data transmitted and received
in the address/data field is the MSB (bit 15). An example access is shown in Figure 10.
Figure 10. Indirect Address Example
Table 8 shows PHY XGXS registers as described in IEEE Draft P802.3ae. The shaded areas are used to indicate
register addresses that are specified in the draft but are not used in this implementation.
There are two vendor supported register ranges. The 4.8000h register range is used for accessing and program-
ming the XGXS registers implemented in the programmable array. All corresponding registers are listed in Table 9.
All PCS embedded core registers can be accessed thru the 4.9xxxh registers shown in Table 10, where the
address is directly mapped to the PCS embedded registers.
Register Descriptions
Table 8. Register Map for XAUI IP Core (Device Address = 4)
Table 9. XAUI IP Core Registers
Control 1 Register
4.0.15
4.0.14
4.0.13
4.0.12
4.0.11
4.0.[10:7]
4.0.6
4.0.[5:2]
Bit(s)
PREAMBLE, 32-BIT
ALL ONES
Reset
Loopback
(not supported)
Speed Selection
Reserved
Low Power
Reserved
Speed Selection
Speed Selection
Name
OP = ADDRESS
ST
00
OP
00
Register Address
PHYADDR
32768 - 65535
0_0000
25 - 32767
1 = PHY XA reset, 0 = Normal operation
Loop back functionality is supported in the PCS core.
The XAUI core does not provide loopback capability.
Value always 0
Value always 0
0= Low Power Mode 1= Normal operation This bit controls
the power_down signal of the XAUI core.
Value always 0
Value always 0
Value always 0
6 - 23
2, 3
DEVICE TYPE = XGXS
24
0
1
4
5
DTYPE
0_0100
TA
PHY XGXS Control 1
PHY XGXS Status 1
PHY XGXS Identifier
Reserved
PHY XGXS Status 2
Reserved
10G PHY XGXS Lane status
Reserved
Vendor specific
0000_1111_0000_0001
REGISTER ADDRESS
TO BE ACCESSED
ADDRESS/DATA
15
Description
PREAMBLE, 32-BIT
Register Name
ALL ONES
ST
00
OP = READ
OP
10
PHYADDR
0_0000
DEVICE TYPE = XGXS
XAUI IP Core User’s Guide
DTYPE
0_0100
TA
0000_1010_0101_1111
R/W S/C
ADDRESS/DATA
DATA RETURNED
R/W
R/W
R
R
R
R
R
R
Reset Value
0
0
0
0
1
0
0
0