XAUI-PM-U1 Lattice, XAUI-PM-U1 Datasheet - Page 3

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XAUI-PM-U1

Manufacturer Part Number
XAUI-PM-U1
Description
Development Software XAUI 10Gb Ethernet
Manufacturer
Lattice
Datasheet

Specifications of XAUI-PM-U1

Tool Type
Development Software Support
Core Architecture
CPLD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lattice Semiconductor
Figure 1. XAUI and XGXS Locations in 10 GbE Protocol Stack
Figure 2. XAUI Solution Simplified Block Diagram
xgmii_tx_data[31:0]
xgmii_tx_ctrl3:0]
xgmii_txclk_156
xgmii_rx_data[31:0]
xgmii_rx_ctrl[3:0]
xgmii_rxclk_156_out
xgmii_rxclk_156
Physical Medium Attachment (PMA)
Physical Medium Dependent (PMD)
Physical Coding Sublayer (PCS)
WAN Interface Sublayer (WIS)*
Media Access Control (MAC)
MAC Control (Optional)
XGMII
XAUI
XGMII
XSBI
MDI
ODDR
IDDR
Reconciliation
Upper Layers
Medium
XGXS*
XGXS*
@156MHz
@156MHz
72b SDR
72b SDR
MDIO
XGMII
XGMII
RX
TX
3
Optional
Optional
XGMII – 10G Medium Independent Interface
XGXS – XAUI Extender Sublayer
XAUI – 10G Attachment Unit Interface
XSBI – 10G 16-Bit Interface
MDI – Medium Dependent Interface
* optional sublayer
Adding the WIS makes the WAN PHY
XAUI IP Core
WAN-compatible framing
Retime, SERDES, CDR
16-bit parallel (OIF)
64b/66b coding
XGMII/XAUI
E/O
FPGA
Array
XAUI IP Core User’s Guide
SERDES
PCS
HDOUT[P:N]0
HDOUT[P:N]1
HDOUT[P:N]2
HDOUT[P:N]3
REFCLK[P:N]
HDIN[P:N]0
HDIN[P:N]1
HDIN[P:N]2
HDIN[P:N]3

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