XAUI-PM-U1 Lattice, XAUI-PM-U1 Datasheet - Page 19

• Manufacturer Part Number: XAUI-PM-U1
• Description: Development Software XAUI 10Gb Ethernet
• Manufacturer: Lattice

Specifications of XAUI-PM-U1

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
XAUI Specifications
Refer to the LatticeECP2M and LatticeECP3 PCS specifications for a complete XAUI timing requirements.
MDIO Specifications
The electrical specifications of the MDIO signals conform to Clause 45.4 of IEEE 802.3ae.
Figure 13. MDIO Timing
Core Generation
The XAUI IP is available for download from the Lattice website at www.latticesemi.com/ip. The IP files are automat-
ically installed using ispUPDATE technology in any user-specified directory.
The ispLEVER
user specifies:
• Project Path - The path to directory where the generated IP files will be loaded.
• File Name - “username” designation given to the generated IP core and corresponding folders and files.
• Design Entry Type - Verilog.
• Device Family - Device family to which IP is to be targeted (e.g., LatticeECP2M). Only families that support the
• Part Name - Specific targeted part within the selected device family.
Note that if IPexpress is called from within an existing project, Project Path, Design Entry, Device Family and Part
Name default to the specified project parameters. Refer to the IPexpress on-line help for further information.
particular core are listed.
MDIO (OUTPUT)
MDIO (INPUT)
Symbol
®
IPexpress™ GUI window is shown in Figure 14. To generate a specific IP core configuration the
t1
t2
t3
t4
t5
t6
MDC
MDC high pulse width
MDC low pulse width
MDC period
MDIO (I) setup to MDC rising edge
MDIO (O) hold time from MDC rising edge
MDIO (O) valid from MDC rising edge
t1
Description
t4
t5
t6
2 t
19
Min.
200
200
400
10
10
0
XAUI IP Core User’s Guide
3 t
Max.
300
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Units
ns
ns
ns
ns
ns
ns