XAUI-PM-U1 Lattice, XAUI-PM-U1 Datasheet - Page 14

• Manufacturer Part Number: XAUI-PM-U1
• Description: Development Software XAUI 10Gb Ethernet
• Manufacturer: Lattice

Specifications of XAUI-PM-U1

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Management Data Input/Output (MDIO) Interface (Optional)
The MDIO interface provides access to the internal XAUI core registers. The register access mechanism corre-
sponds to Clause 45 of IEEE 802.3ae. The XAUI core provides access to XGXS registers 0x0000-0x0024 as spec-
ified in IEEE 802.3ae. Additional registers in the vendor-specific address space have been allocated for
implementation-specific control/status functions.
The physical interface consists of two signals: MDIO to transfer data/address/control to and from the device, and
MDC, a clock up to 2.5 MHz sourced externally to provide the synchronization for MDIO. The fields of the MDIO
transfer are shown in Figure 9.
Figure 9. Fields of MDIO Protocol
Management Frame Structure
Each management data frame consists of 64 bits. The first 32 bits are preamble consisting of 32 contiguous 1s on
the MDIO. Following the preamble is the start-of-frame field (ST) which is a 00 pattern. The next field is the opera-
tion code (OP) that is shown in Figure 9.
The next two fields are the port address (PRTAD) and device type (DTYPE). Since the physical layer function in 10
GbE is partitioned into various logical (and possibly separate physical) blocks, two fields are used to access these
blocks. The PRTAD provides the overall address to the PHY function. The first port address bit transmitted and
received is the MSB of the address. The DTYPE field addresses the specific block within the physical layer func-
tion.
Device address zero is reserved to ensure that there is not a long sequence of zeros. If the ST field is 01 then the
DTYPE field is replaced with REGAD (register address field of the original clause 22 specification). The XAUI core
does not respond to any accesses with ST = 01.
The TA field (Turn Around) is a 2-bit turnaround time spacing between the device address field and the data field to
avoid contention during a read transaction. The TA bits are treated as don’t cares by the XAUI core.
During a write or address operation, the address/data field transports 16 bits of write data or register address
depending on the access type. The register is automatically incremented after a read increment. The address/data
field is 16 bits.
OP
00
01
10
11
ST=00
ADDRESS
WRITE
READ INCREMENT
READ
ACCESS TYPE
ST
2b
OP
2b
PRTAD
5b
VALUE
16-31
6-15
0
1
2
3
4
5
RESERVED
10G PMA/PMD
10G WIS
10G PCS
10G PHY XGXS
10G DTE XGXS
RESERVED
VENDOR SPECIFIC
DTYPE*
DEVICE TYPE
5b
* If ST=01, this field is REGAD (register address).
14
TA
2b
ADDRESS
WRITE
READ INCREMENT
READ
ACCESS TYPE
ADDRESS/DATA
16b
XAUI IP Core User’s Guide
RESERVED
10G PMA/PMD
10G WIS
10G PCS
CONTENTS