EVAL-AD9880-ABZ Analog Devices Inc, EVAL-AD9880-ABZ Datasheet - Page 23

• Manufacturer Part Number: EVAL-AD9880-ABZ
• Description: Video Input Module Kit AD9880
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD9880-ABZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9880
• Primary Attributes: HDMI Receiver & Analog Interface
• Secondary Attributes: Triple 8-bit 150MSPS ADC's
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2-WIRE SERIAL REGISTER MAP
The AD9880 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to
write and read the control registers through the 2-wire serial interface port.
Table 11. Control Register Map
Hex
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
Read/Write
or Read Only
Read
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Bits
[7:0]
[7:0]
[7:4]
[7:6]
[5:3]
[2]
[7:3]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:2]
[7:2]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Default
Value
00000000
01101001
1101****
01******
**001***
*****0**
10000***
10000000
10000000
10000000
00000000
10000000
00000000
10000000
00000000
10000000
00100000
010000**
010000**
0*******
*0******
**0*****
***0****
****0***
*****0**
******0*
*******0
Register Name
Chip Revision
PLL Divider MSB
PLL Divider
VCO Range
Charge Pump
External Clock Enable
Phase Adjust
Red Gain
Green Gain
Blue Gain
Red Offset Adjust
Red Offset
Green Offset Adjust
Green Offset
Blue Offset Adjust
Blue Offset
Sync Separator
Threshold
SOG Comparator
Threshold Enter
SOG Comparator
Threshold Exit
Hsync Source
Hsync Source
Override
Vsync Source
Vsync Source
Override
Channel Select
Channel Select
Override
Interface Select
Interface Override
Rev. 0 | Page 23 of 64
Description
Chip revision ID. Revision is read [7:4]. [3:0].
PLL feedback divider value MSB.
PLL feedback divider value.
VCO range.
Charge pump current control for PLL.
Selects the external clock input rather that the internal PLL
clock.
Selects the clock phase to use for the ADC clock.
Controls the gain of the red channel PGA. 0 = low gain,
255 = high gain.
Controls the gain of the green channel PGA. 0 = low gain,
255 = high gain.
Controls the gain of the blue channel PGA. 0 = low gain,
255 = high gain.
User adjustment of auto offset. Allows user control of brightness.
Red offset/target code. 0 = small offset, 255 = large offset.
User adjustment of auto offset. Allows user control of brightness.
Green offset/target code. 0 = small offset, 255 = large offset.
User adjustment of auto offset. Allows user control of brightness.
Blue offset/target code. 0 = small offset, 255 = large offset.
Selects the maximum Hsync pulse width for composite sync
separation.
The enter level for the SOG slicer. Must be less than or equal to
the exit level.
The exit level for the SOG slicer. Must be greater than or equal to
the enter level.
0 = Hsync.
1 = SOG.
0 = auto Hsync source.
1 = manual Hsync source.
0 = Vsync.
1 = Vsync from SOG.
0 = auto Hsync source.
1 = manual Hsync source.
0 = Channel 0.
1 = Channel 1.
0 = autochannel select.
1 = manual channel select.
0 = analog interface.
1 = digital interface.
0 = auto-interface select.
1 = manual interface select.
AD9880