EVAL-AD9880-ABZ Analog Devices Inc, EVAL-AD9880-ABZ Datasheet - Page 26

• Manufacturer Part Number: EVAL-AD9880-ABZ
• Description: Video Input Module Kit AD9880
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD9880-ABZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9880
• Primary Attributes: HDMI Receiver & Analog Interface
• Secondary Attributes: Triple 8-bit 150MSPS ADC's
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9880
Hex
Address
0x22
0x23
0x24
0x25
Read/Write
or Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Bits
[6]
[5]
[4]
[3]
[2]
[7:0]
[7:0]
[7]
[6]
[5]
[4]
[3]
[2:1]
[0]
[7:6]
[5:4]
[3:2]
Default
Value
*1******
**0*****
***0****
**** 1***
**** *1**
4
32
1*******
*1******
**1*****
***1****
****1***
*****11*
*******0
01******
**11****
****00**
Register Name
PLL Sync Filter Enable
Vsync Filter Enable
Vsync Duration
Enable
Auto Offset Clamp
Mode
Auto Offset Clamp
Length
Vsync Duration
Hsync Duration
Hsync Output
Polarity
Vsync Output Polarity
DE Output Polarity
Field Output Polarity
SOG Output Polarity
SOG Output Select
Output CLK Invert
Output CLK Select
Output Drive
Strength
Output Mode
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Selects which pins the data comes out on.
Description
Enables the PLL to use the filtered Hsync rather than the raw
Hsync. This clips any bad Hsyncs, but does not regenerate
missing pulses.
Enables the Vsync filter. The Vsync filter gives a predictable
Hsync/Vsync timing relationship but clips one Hsync period off
the leading edge of Vsync.
Enables the Vsync duration block. This block can be used if
necessary to restore the duration of a filtered Vsync.
0 = auto offset measures code during clamp.
1 = auto offset measures code (10 or 16) clock cycles after end of
clamp for 6 clock cycles.
Sets delay after end of clamp for auto offset clamp mode = 1.
0 = Delay is 10 clock cycles.
1 = Delay is 16 clock cycles.
Vsync Duration.
Hsync Duration. Sets the duration of the output Hsync in pixel
clocks.
Output Hsync Polarity (both DVI and Analog). 0 = active low out.
1 = active high out.
Output Vsync polarity (both DVI and analog).
0 = active low out.
1 = active high out.
Output DE polarity (both DVI and analog) .
0 = active low out.
1 = active high out.
Output field polarity (both DVI and analog).
0 = active low out.
1 = active high out.
Output SOG polarity (analog only).
0 = active low out.
1 = active high out.
Selects signal present on SOG output.
00 = SOG (SOG0 or SOG1).
01 = Raw Hsync (HSYNC0 or HSYNC1).
10 = Regenerated sync.
11 = Hsync to PLL.
0 = Don’t invert clock out.
1 = Invert clock out.
Select which clock to use on output pin. 1× CLK is divided down
from TMDS clock input when pixel repetition is in use.
00 = ½× CLK.
01 = 1× CLK.
10 = 2× CLK.
11 = 90° phase 1X CLK.
Set the drive strength of the outputs.
00 = lowest, 11 = highest.
00 = 4:4:4 mode (normal).
01 = 4:2:2 + DDR 4:2:2 on blue.
10 = DDR 4:4:4 + DDR 4:2:2 on blue.