EVAL-AD9880-ABZ Analog Devices Inc, EVAL-AD9880-ABZ Datasheet - Page 30

• Manufacturer Part Number: EVAL-AD9880-ABZ
• Description: Video Input Module Kit AD9880
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD9880-ABZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9880
• Primary Attributes: HDMI Receiver & Analog Interface
• Secondary Attributes: Triple 8-bit 150MSPS ADC's
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9880
Hex
Address
0x50
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5E
0x5F
0x60
0x61
Read/Write
or Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read
Read
Read
Read
Read
Read
Bits
[7:0]
[7:0]
[7]
[6]
[3]
[2]
[7]
[6:4]
[3]
[2:0]
[6]
[5]
[4]
[2]
[1]
[0]
[6:0]
[3]
[7:6]
[5:3]
2
1
0
[7:0]
[7:4]
[3:0]
[5:4]
[3:0]
Default
Value
00100000
00001111
0*******
*0******
****0***
*****0**
Channel Status
Clock Accuracy
Register Name
Test
Test
A/V Mute Override
AV Mute Value
Disable Video Mute
Disable Audio Mute
MCLK PLL Enable
MCLK PLL_N
N_CTS_Disable
MCLK FS_N
MDA/MCL PU
CLK Term O/R
Manual CLK Term
FIFO Reset UF
FIFO Reset OF
MDA/MCL Three-
State
Packet Detected
HDMI Mode
Channel Status
Category Code
Channel Number
Source Number
Sampling
Audio Channel Status
Rev. 0 | Page 30 of 64
Clock termination power-down override 0 = auto, 1 = manual.
Clock termination: 0 = normal, 1 = disconnected.
Mode = 00. All others are reserved.
Description
Must be written to 0x20 for proper operation.
Must be written to default 0x0F for proper operation.
A1 overrides the AV mute value with Bit 6.
Sets AV mute value if override is enabled.
Disables mute of video during AV mute.
Disables mute of audio during AV mute.
MCLK PLL enable—uses analog PLL.
MCLK PLL N [2:0]—this controls the division of the MCLK out of
the PLL: 0 = /1, 1 = /2, 2 = /3, 3 = /4, etc.
Prevents the N/CTS packet on the link from writing to the N and
CTS registers.
Controls the multiple of 128 fs used for MCLK out . 0 = 128 fs,
1 = 256 fs, 2 = 384, 7 = 1024 fs.
This disables the MDA/MCL pull-ups.
This bit resets the audio FIFO if underflow is detected.
This bit resets the audio FIFO if overflow is detected.
This bit three-states the MDA/MCL lines.
These 7 bits are updated if any specific packet has been received
since last reset or loss of clock detect. Normal is 0x00.
Bit Data Packet Detected
0
1
2
3
4
5
6
0 = DVI, 1 = HDMI.
When Bit 1 = 0 (Linear PCM).
000 = 2 audio channels without pre-emphasis.
001 = 2 audio channels with 50/15 μs pre-emphasis.
010 = reserved.
011 = reserved.
0 = Software for which copyright is asserted.
1 = Software for which no copyright is asserted.
0 = audio sample word represents linear PCM samples.
1 = audio sample word used for other purposes.
0 = consumer use of channel status block.
Clock accuracy.
00
01
10
11
0011
AVI infoframe.
Audio infoframe.
SPD infoframe.
MPEG source infoframe.
ACP packets.
ISRC1 packets.
ISRC2 packets.
= Level II.
= Level III.
= Level I.
= reserved.
=
32 kHz.