EVAL-AD9880-ABZ Analog Devices Inc, EVAL-AD9880-ABZ Datasheet - Page 46

• Manufacturer Part Number: EVAL-AD9880-ABZ
• Description: Video Input Module Kit AD9880
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD9880-ABZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9880
• Primary Attributes: HDMI Receiver & Analog Interface
• Secondary Attributes: Triple 8-bit 150MSPS ADC's
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9880
Table 56. SOGOUT Three-State
Select
0
1
0x26
Table 57. Power-Down Input Polarity
Select
0
1
0x26
Table 58. Power Down Pin Function
PWRDN
Pin
Function
00
01
10
11
0x26
Table 59. Power-Down Settings
Select
0
1
0x27
3
This bit defines the polarity of the input power-down
pin. The power-up default setting is 1.
2-1
These bits define the different operational modes of
the power-down pin. These bits are functional only
when the power-down pin is active; when it is not
active, the part is powered up and functioning. The
power-up default setting is 00.
0
This bit is used to put the chip in power-down mode.
In this mode the chips power dissipation is reduced to
a fraction of the typical power (see Table 1 for exact
power dissipation). When in power-down, the
HSOUT, VSOUT, DATACK, and all 30 of the data
outputs are put into a high impedance state. Note that
the SOGOUT output is not put into high impedance.
Circuit blocks that continue to be active during
power-down include the voltage references, sync
processing, sync detection, and the serial register.
These blocks facilitate a fast start-up from power-
down. The power-up default setting is 0.
7
This bit enables the chip to go into low power mode,
or seek mode if no sync inputs are detected. The
power-up default setting is 1.
Result
Normal I2S output
I2S pins in high impedance mode.
Result
The chip is powered down and all outputs except
SOGOUT are in high impedance mode.
The chip is powered down and all outputs are in
high impedance mode.
The chip remains powered up, but all outputs
except SOGOUT are in high impedance mode.
The chip remains powered up, but all outputs are
in high impedance mode.
Result
Power-down pin is active low
Power-down pin is active high
Power-Down Polarity
Power-Down Pin Function
Power-Down
Auto Power-Down Enable
Result
Normal operation
Power-Down
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Table 60. Auto Power-Down Select
Auto
Power Down
0
1
0x27
0x27
Table 61. MCLK External Select
Select
0
1
BT656 GENERATION
0x27
Table 62. BT656 Mode
Select
0
1
0x27
Table 63. DE Generation
Select
0
1
0x27
0x28
6
This bit sets the LSB of the address of the HDCP I
This should be set to 1 only for a second receiver in a
dual-link configuration. The power-up default is 0.
5
This bit enables the MCLK to be supplied externally. If
an external MCLK is used, then it must be locked to
the video clock according to the CTS and N available
in the I
and the input MCLK results in dropped or repeated
audio samples. The power-up default setting is 0.
4
This bit enables the output to be BT656-compatible
with defined start of active video (SAV) and end of
active video (EAV) controls to be inserted. These
require specification of the number of active lines,
active pixels per line, and delays to place these
markers. The power-up default setting is 0.
3
This bit allows the use of the internal DE generator in
DVI mode. The power-up default setting is 0.
2-0
These bits define the offset in Hsyncs from Field 0 to
Field 1. The power-up default setting is 000.
7-2
These bits set the delay (in lines) from the leading
edge of Vsync to active video. The power-up default
setting is 24.
Result
Internal DE generation disabled
Force DE generation via programmed registers
Result
Use internally generated MCLK
Use external MCLK input
Disable BT656 video mode
Enable BT656 video mode
Result
2
C. Any mismatch between the internal MCLK
HDCP A0 Address
MCLK External Enable
BT656 Enable
Force DE Generation
Interlace Offset
Vsync Delay
Result
Auto power down disabled
Chip powers down if no sync inputs present
2
C.