EVAL-AD9880-ABZ Analog Devices Inc, EVAL-AD9880-ABZ Datasheet - Page 8

• Manufacturer Part Number: EVAL-AD9880-ABZ
• Description: Video Input Module Kit AD9880
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD9880-ABZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9880
• Primary Attributes: HDMI Receiver & Analog Interface
• Secondary Attributes: Triple 8-bit 150MSPS ADC's
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9880
Pin Type
OUTPUTS
REFERENCES
POWER SUPPLY
CONTROL
HDCP
AUDIO DATA OUTPUTS
DIGITAL VIDEO DATA
DIGITAL VIDEO CLOCK INPUTS
DATA ENABLE
RTERM
57
35
Pin No.
92 to 99
2 to 9
12 to 19
89
87
85
86
84
80, 76, 72,
67, 45, 33
100, 90, 10
59, 56, 54
48, 32, 30
83
82
49
50
51
52
28
27
26
25
24
20
21
22
23
34
38
37
41
40
43
44
88
46
Mnemonic
RED [7:0]
GREEN [7:0]
BLUE [7:0]
DATACK
HSOUT
VSOUT
SOGOUT
O/E FIELD
FILT
V
V
PV
DV
GND
SDA
SCL
DDC_SCL
DDC_SDA
MCL
MDA
S/PDIF
I2S0
I2S1
I2S2
I2S3
MCLKIN
MCLKOUT
SCLK
LRCLK
Rx0+
Rx0−
Rx1+
Rx1−
Rx2+
Rx2−
RxC+
RxC−
DE
RTERM
D
DD
DD
DD
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Function
Outputs of Red Converter, Bit 7 is MSB
Outputs of Green Converter, Bit 7 is MSB
Outputs of Blue Converter, Bit 7 is MSB
Data Output Clock
HSYNC Output Clock (Phase-Aligned with DATACK)
VSYNC Output Clock (Phase-Aligned with DATACK)
SOG Slicer Output
Odd/Even Field Output
Connection For External Filter Components For PLL
Analog Power Supply and DVI Terminators
Output Power Supply
PLL Power Supply
Digital Logic Power Supply
Ground
Serial Port Data I/O
Serial Port Data Clock
HDCP Slave Serial Port Data Clock
HDCP Slave Serial Port Data I/O
HDCP Master Serial Port Data Clock
HDCP Master Serial Port Data I/O
S/PDIF Digital Audio Output
I
I
I
I
External Reference Audio Clock In
Audio Master Clock Output
Audio Serial Clock Output
Data Output Clock For Left And Right Audio Channels
Digital Input Channel 0 True
Digital Input Channel 0 Complement
Digital Input Channel 1 True
Digital Input Channel 1 Complement
Digital Input Channel 2 True
Digital Input Channel 2 Complement
Digital Data Clock True
Digital Data Clock Complement
Data Enable
Sets Internal Termination Resistance
2
2
2
2
S Audio (Channels 1, 2)
S Audio (Channels 3, 4)
S Audio (Channels 5, 6)
S Audio (Channels 7, 8)
Value
V
V
V
V
V
V
V
V
3.3 V
1.8 V to 3.3 V
1.8 V
1.8 V
0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
V
V
V
V
V
V
V
V
V
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
3.3 V CMOS
500Ω
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD